Timing recovery circuit and method in automatic equalizer

Details Timing recovery circuit and method in automatic equalizer Timing recovery circuit and method in automatic equalizer

2000-07-07

2004-03-09

Fan, Chieh M. (Department: 2634)

Pulse or digital communications

Receivers

Angle modulation

C375S230000, C375S354000

Reexamination Certificate

active

06704373

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a timing recovery circuit in an automatic equalizer or the like and a timing recovery method in the same. More particularly, the present invention concerns a timing recovery performed in an automatic equalizer, in which code decision is performed by sequence estimation.
Among the automatic equalizers in which code decision is performed by system estimation, is one of DDFSE (Delayed Decision Feedback Sequence Estimation) type. As a prior art DDFSE timing recovery method is one, in which a timing is selected such as to correspond to a maximum value of an evaluation function which is used for precursor component estimation and constituted by a division of total impulse response power level as numerator by truncation error, i.e., sum of the total impulse response power level and thermal noise power level, as denominator.
A timing recovery method which is described in IEEE Journal of Selected Areas in Communications, vol. 15, pp. 5-15, January, 1997, will now be described with reference to FIG.
4
. In this method, thermal noise power level S
tno
is first determined according to the intensity of received signal S
r
(Step
401
). Then, by using the total power level of 1-st to (i−1)-th (i being a natural number) ones of L impulse response signals S
ir
as truncation power signal level S
tpow
and the total Power level of i-th to (i+m−1)-th (m being a natural number) ones of S
ir
as precursor power signal level S
prpow
, a value of that corresponds to the maximum value of
S
prpow
/(
S
tpow
+S
tno
)
is determined and set as i max. (step
402
).
Then, by using m, i.e., i
max
.-th to (i
max
.+m−1)-th, ones of S
ir
as precursor response set S
prres
, n, i.e., i
max
.-th to (i
max
.+m+n−1)-th, ones of S
ir
are set as postcursor response signal set S
pores
(step
403
). In this way, the timing recovery is executed.
The above timing recovery circuit, however, has a drawback that it is necessary to perform computations concerning the evaluation function including the division as noted above for each timing.
SUMMARY OF THE INVENTION
The present invention was made in order to overcome the above drawback, and its object is to provide timing recovery circuit in an automatic equalizer and a timing recovery method in the same, which are free from computations concerning any evaluation function.
According to a first aspect of the present invention, there is provided a timing recovery circuit comprising: absolute response value signal generating means for obtaining the absolute values of L input impulse response value signals representing as communication channel characteristic and arranged in the order of shorter response times and providing the obtained absolute values as absolute response value signals; absolute value signal sum generating means for using the maximum one of the absolute response value signals as the maximum absolute response value signal and m sequential absolute response value signals, in which the maximum absolute response value signal is highest in response speed, as a precursor candidate signal set and providing the total sum of the precursor candidate signal set as an absolute value signal sum; weighted absolute value signal sum generating means for multiplying the absolute value signal sum by a shift factor determined on the basis of the received signal intensity to obtain and provide a weighted absolute value signal sum; precursor/postcursor response signal set generating means for providing, when the weighted signal sum is greater than all of preceding absolute response value signals as the absolute response value signals higher in response speed than the precursor candidate signal set, m impulse response signals corresponding to the precursor candidate signal set among the L impulse response signals as a precursor response set and n impulse response signals next in response speed to the precursor response set as a postcursor response signal set; and weighted absolute value signal sum updating means for updating, when the weighted signal sum is less than any one of the preceding absolute value response signal sum, the precursor candidate signal set with m sequential absolute response value signals higher in response speed by one each and the weighted absolute value signal sum with the total sum of the updated precursor candidate signal set, the precursor and postcursor response signal sets being determined recursively.
According to a second aspect of the present invention, there is provided a timing recovery circuit comprising: absolute response value signal generating means for obtaining the absolute values of L input impulse response value signals representing as communication channel characteristic and arranged in the order of shorter response times and providing the obtained absolute values as absolute response value signals; truncation error signal generating means for using the maximum one of the absolute response value signals as the maximum absolute response value signal and m sequential absolute response value signals, in which the maximum absolute response value signal is highest in response speed, as a precursor candidate signal set, providing the total sum of the precursor candidate signal set as an absolute value signal sum and providing the total sum of the all the absolute response value signals higher in response speed than the maximum absolute response value signal as a truncation error signal; weighted absolute value signal sum generating means for multiplying the absolute value signal sum by a shift factor determined on the basis of the received signal intensity to obtain and provide a weighted absolute value signal sum; precursor/postcursor response signal set generating means for providing, when the weighted signal sum is greater than the truncation error signal, m impulse response signals corresponding to the precursor candidate signal set among the L impulse response signals as a precursor response set and n impulse response signals next in response speed to the precursor response set as a postcursor response signal set; and truncation error signal updating means for updating, when the weighted signal sum is less than the truncation error signal, the precursor candidate signal set with the m sequential absolute response value signals higher in response speed by one each, the weighted absolute value signal sum with the total sum of the updated precursor candidate signal set and the truncation error signal with the total sum of the all the absolute response value signals higher in response speed than the updated precursor candidate signals, the precursor and postcursor response sets being determined recursively.
According to a third aspect of the present invention, there is provided a timing recovery circuit comprising: absolute response value signal generating means for obtaining the absolute values of L input impulse response value signals representing as communication channel characteristic and arranged in the order of shorter response times and providing the obtained absolute values as absolute response value signals; precursor candidate signal generating means for using the maximum one of the absolute response value signals as the maximum absolute response value signal and m sequential absolute response value signals, in which the maximum absolute response value signal is highest in response speed, as a precursor candidate signal set; weighted absolute value signal generating means for multiplying the maximum absolute response value signal by a shift factor determined on the basis of the received signal intensity to obtain and provide a weighted absolute value signal; precursor/postcursor response value signal set generating means for providing, when the weighted signal is greater than all of preceding absolute response value signals as the absolute response value signals higher in response speed than the precursor candidate signal set, m impulse response value signals corresponding to the precursor candidate signal set among the L

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