Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2007-03-06
2007-03-06
Tran, Khanh (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
Reexamination Certificate
active
10438875
ABSTRACT:
A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.
REFERENCES:
patent: 5235622 (1993-08-01), Yoshida
patent: 6128357 (2000-10-01), Lu et al.
patent: 6504869 (2003-01-01), Yedid
patent: 6529549 (2003-03-01), Norrell et al.
patent: 6667640 (2003-12-01), Asano
Rabin & Berdo P.C.
Tran Khanh
LandOfFree
Timing recovery circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Timing recovery circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing recovery circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3753175