Timing phase synchronization detecting circuit and demodulator

Details Timing phase synchronization detecting circuit and demodulator Timing phase synchronization detecting circuit and demodulator

1998-10-22

2000-08-01

Chin, Stephen

Pulse or digital communications

Receivers

Angle modulation

375360, 375371, 375373, H04L 2714

Patent

active

060977663

ABSTRACT:
A demodulator is made compact, and with a simple circuit arrangement, and also having a better bit error rate characteristic. A timing phase synchronization detecting circuit 219 judges any one of the following two conditions based upon baseband phase data 202, i.e., an UNLOCK (timing phase asynchronous) condition, and a LOCK (timing phase synchronous) condition. Based upon the judgement result of the timing phase synchronization detecting circuit 219, in a timing recovering means 221, a frequency range of a PLL (phase synchronization loop) is variable, whereas the number of data entered within 1 symbol time is variable in a frequency synchronizing means 222 and a carrier recovering means 223. A data demodulating means 224 outputs demodulation data 206 in response to baseband phase data 202 and a recovery carrier signal 205.

REFERENCES:
patent: 4633193 (1986-12-01), Scordo
patent: 4675558 (1987-06-01), Serrone et al.
patent: 5235622 (1993-08-01), Yoshida
patent: 5400370 (1995-03-01), Guo
patent: 5563891 (1996-10-01), Wang
patent: 5651031 (1997-07-01), Ishizu
Yamamoto et al, "Arrangement and Characteristics of 384 kbps-/4 Shift QPSK Burst Demodulator", Japanese Telecommunication Institute Technical Report RCS 92-100, (1993-01), pp. 7-12.
Saito et al, "Adaptive Carrier Synchronization (ACT) Demodulation System for QPSK Mobile Wireless Transmission", Japanese Telecommunication Institute Report vol. J75-B-II No.8, Aug. 1992, pp. 499-507.

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