Timing of and minimizing external influences on digital signals

Details Timing of and minimizing external influences on digital signals Timing of and minimizing external influences on digital signals

2005-10-18

2005-10-18

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S141000, C365S195000

Reexamination Certificate

active

06956424

ABSTRACT:
The performance of digital signals depends to a great extent on the frequency. However, the higher the frequency, the shorter the remaining time, in which digital signals can be reliably received by a receiver from a driver via a printed conductor. The run time of the clock pulse and signals must be optimized in such a way that no timing losses occur at any location, even in the extreme environmental conditions. The invention improves the timing and minimizes external influences by coupling the output signals to an internal PLL clock pulse.

REFERENCES:
patent: 6003118 (1999-12-01), Chen
patent: 2002/0114195 (2002-08-01), Ahn et al.

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