Timing method and apparatus for integrated circuit device

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S141000, C327S156000, C327S158000, C326S093000, C326S096000, C365S049130

Reexamination Certificate

active

06933757

ABSTRACT:
According to one embodiment, a timing circuit (300) can include a first control circuit (302), a first clocked circuit (304), a second clocked circuit (306), and a second control circuit (314). A first control circuit (302) may compensate for a first timing signal FCLK making a transition earlier in time than a second timing signal RCLK. A second control circuit (314) may compensate for a second timing signal RCLK making a transition earlier in time than a first timing signal FCLK. A first timing signal FCLK can be a periodic signal generated by a first PLL type circuit (310) in response to a falling edge of an external clock signal EXT CLK. A second timing signal RCLK can be a periodic signal generated by a second PLL type circuit (312) in response to a rising edge of an external clock signal EXT CLK.

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