Timing gradient smoothing circuit in a synchronous read channel

Details Timing gradient smoothing circuit in a synchronous read channel Timing gradient smoothing circuit in a synchronous read channel

1995-08-29

1996-11-19

Psitos, A.

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

375354, G11B 5301

Patent

active

055769047

ABSTRACT:
In a synchronous read channel for magnetic recording, a timing recovery phase-locked loop (PLL) comprises a technique for smoothing a timing gradient .DELTA.t computed from estimated sample values and actual sample values. If an estimated sample value for computing the timing gradient is zero, then the timing gradient is increased, and if all of the estimated sample values for computing the timing gradient are zero, then the timing gradient is copied from its prior value. Smoothing the timing gradient reduces gain variations in the PLL and results in more effective timing recovery.

REFERENCES:
patent: 4890299 (1989-11-01), Dolivo et al.
patent: 5303269 (1994-04-01), Altes
patent: 5465059 (1995-11-01), Pan et al.

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