Timing generator circuit including adjustable tapped delay line

Details Timing generator circuit including adjustable tapped delay line Timing generator circuit including adjustable tapped delay line

1990-10-24

1992-10-27

Howell, Janice A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307594, 307595, 307597, 307601, 307602, 307603, 307605, 307606, 328 55, 328 63, 328 66, 328 72, H03K 5159, H03K 700, H03K 301, H03K 1700

Patent

active

051592053

ABSTRACT:
A circuit for generating a plurality of timing signals includes a plurality of cascade-connected delay cells, each having an input coupled to an output of another, and a plurality of latches. Set inputs of various latches are coupled to outputs of various delay cells to determine times of occurrence of leading edges of various timing pulses. Reset inputs of the various latches are coupled to outputs of various delay cells to determine times of occurrence of trailing edges of various timing pulses. The circuit includes a phase detector having a first input coupled to receive a clock signal and a second input coupled to an output of one of the delay cells to receive a signal indicative of propagation of a logic state through a first group of the delay cells, to produce an adjustment signal indicative of whether the phase of the indicator signal is ahead of or behind the phase of the clock signal. Each of the delay cells increases or decreases propagation time through that delay cell in response to the adjustment signal, so as to cause a time required for the logic state to propagate through all of the delay cells to be equal to a period of the clock signal.

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