Timing generator and semiconductor test apparatus

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

Reexamination Certificate

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C327S293000, C327S295000

Reexamination Certificate

active

07944263

ABSTRACT:
A timing generator reduces operation-dependent power consumption (AC component) and noises generated from a clock distribution circuit itself in distributing a clock, and further reduces a skew attributed to the clock distribution. A clock distribution circuit20for distributing the clock to timing generating sections10-1to10-n has a clock main path21connected to a main path buffer24and a clock return path26connected to a return path buffer27. A load capacity of the main path buffer24is equal to that of the return path buffer27. Biases of the buffers are the same potential and are generated by a delay locked-loop circuit30. A propagation delay time of the clock distribution circuit is controlled so as to be an integral multiple of a clock period.

REFERENCES:
patent: 5670899 (1997-09-01), Kohdaka
patent: 6046607 (2000-04-01), Kohdaka
patent: 6111448 (2000-08-01), Shibayama
patent: 6191632 (2001-02-01), Iwata et al.
patent: 7023252 (2006-04-01), Schultz
patent: 2005/0110544 (2005-05-01), Suda et al.
patent: 08-94725 (1996-04-01), None
patent: 08-320360 (1996-12-01), None
patent: 11-511565 (1999-10-01), None
patent: 2001-235521 (2001-08-01), None
patent: 2002-267725 (2002-09-01), None

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