Timing generator

Details Timing generator Timing generator

1988-02-26

1990-06-12

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375106, 331 49, 328 63, H04L 704

Patent

active

049339559

ABSTRACT:
The circuitry of the present invention taps a DS0 data stream and outputs a timing signal to drive terminal multiplexers. Even if the data bit stream is lost, the present invention continues to provide proper clocking signals. A composite clock (bit and byte clock) is provided by the present invention with the bit clock at 64 KHz and the byte clock at 8 KHz in the preferred embodiment. To avoid the problem of phase shift over long distances (limiting cable length) the present invention phase adjusts the digital bit stream clocking signal with a 360 degree delay, giving the appearance of advancing the signal in phase. An additional delay of one frame width is applied to the signal. A negative phase delay equivalent to cable runs from 0-1500 feet in 500 foot increments is also applied. In the preferred embodiment, a shift register is tapped in reverse order to accomplish this phase delay.

REFERENCES:
patent: 3629503 (1969-04-01), Rempert
patent: 3940558 (1976-02-01), Gabbard et al.
patent: 4630291 (1986-12-01), Lankar et al.
patent: 4685101 (1987-08-01), Segal et al.
patent: 4694472 (1987-09-01), Torok et al.
patent: 4805195 (1989-02-01), Keegan

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