Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2005-05-17
2005-05-17
Eisen, Alexander (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S205000
Reexamination Certificate
active
06894674
ABSTRACT:
A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.
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JP07-287208 (SONY-208) computer translation.*
JP 2000-075842 (SONY-842) translation.*
JP 2000-305527 (SEIKO-527) translation.*
JP2000-227608 (HITACHI) translation.*
JP08-166775 (SHARP) translation.*
JP 2000-122575 (CASIO) translation.*
International Search Report.
Maekawa Toshikazu
Maki Yasuhito
Nakajima Yoshiharu
Eisen Alexander
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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