Timing generation circuit for an electro-optic oscilloscope

Details Timing generation circuit for an electro-optic oscilloscope Timing generation circuit for an electro-optic oscilloscope

1999-06-02

2001-09-11

Brown, Glenn W. (Department: 2858)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Analysis of complex waves

C324S076250, C324S076260, C324S076360

Reexamination Certificate

active

06288529

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electro-optic sampling oscilloscope that carries out measurement of a measured signal by using a optical pulse generated based on a timing signal from a timing generation circuit, and in particular to an electro-optic sampling oscilloscope designed to improve the timing generation circuit that generates the timing signal.
This application is based on Japanese Patent Application, No. Hei 10-155046 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
It is possible to couple an electrical field generated by a measured signal with an electro-optic crystal, input a laser light into this electro-optic crystal, and observe the waveform of the measured signal by the state of the polarization of the laser light. The electro-optic sampling oscilloscope (hereinbelow, referred to as an EOS oscilloscope) exploits this phenomenon by using an electro-optic probe that can pulse the laser light, and observe with an extremely high time resolution when sampling the measured signal.
When this electro-optic sampling oscilloscope (hereinbelow, referred to as an “EOS oscilloscope”) is compared to a conventional sampling oscilloscope that uses an electrical probe, the following characteristics have received much attention:
1. It is easy to observe the signal because a ground wire is unnecessary.
2. Because the metal pins at the end of the electro-optic probe are insulated from the circuit system, it is possible to realize high input impedance, and as a result of this, there is almost no degradation of the state of the measured point.
3. By using an optical pulse, broadband measurement up to the GHz order is possible.
Next, the structure of an EOS oscilloscope will be explained referring to FIG.
3
. The EOS oscilloscope is structured from an EOS oscilloscope main body
1
and an electro-optic probe
2
. In the main body
1
of the EOS oscilloscope, the trigger circuit
3
receives a signal from the outside, and outputs a trigger signal that marks the beginning of measurement of a measured signal. The timing generation circuit
4
generates the timing of an optical pulse and the timing for A/D conversion, and the optical pulse generation circuit
5
generates an optical pulse based on the timing signal from the timing generation circuit
4
. The optical pulse from the optical pulse generation circuit
5
is supplied to the electro-optic probe
2
, and is subject to a change in polarization by an electro-optic element. The polarization of the polarized optical pulse is detected in the electro-optic probe
2
, and it is converted into an electric signal. This signal is input into on the EOS oscilloscope main body
1
, amplification and A/D conversion of the signal are carried out by the A/D conversion circuit
6
, processing of the signal that has become the object of measurement for display, etc., is carried out by the processing circuit
7
, and it is displayed on the display
8
.
FIG. 4
is a block diagram showing an example of the conventional structure of the timing generation circuit
4
. In
FIG. 4
, reference numeral
41
is a fast ramp circuit wherein the trigger signal Str is used as a trigger, and the amplified ramp waveforms are output sequentially. Reference numeral
42
is a slow ramp circuit comprising a counter
42
a
that increments the input signals and a D/A conversion circuit that D/A converts and outputs the count value of this counter
42
a
. Reference numeral
43
is a comparator circuit that compares the output of the fast ramp circuit
41
and the output of the slow ramp circuit
42
, and outputs the timing signal Stm when they agree. This timing signal Stm becomes the output signal of the timing generation circuit
4
. In addition, the timing signal Stm is input into the counter
42
a.
Next, the operation of the timing generation circuit
4
shown in if
FIG. 4
will be explained referring to FIG.
5
. First, the fast ramp circuit
41
outputs a ramp waveform when the trigger signal Str is input (refer to FIG.
5
(
b
)). At the same time, in the slow ramp circuit
42
, when the output of the comparator circuit
43
is input, the counter
42
a
is incremented by
1
, and this count value is made into an analogue value by the D/A conversion circuit
42
b
, and output. Thereby, each time the output of the comparator circuit
43
is input, a step-shaped waveform is generated (refer to FIG.
5
(
c
)). The comparator circuit
43
compares the output of the fast ramp circuit
41
and the output of the slow ramp circuit
42
, and after the trigger signal Str is input and rises to the point they agree the first time, outputs a pulse having a pulse width of a specified time (refer to FIG.
5
(
d
)). This becomes the timing signal Stm.
In its initial state, because the output of the fast ramp circuit
41
and the output of the slow ramp circuit
42
are zero, the rise of the timing signal Stm is almost simultaneous with the rise of the trigger signal Str. Subsequently, because the output of the slow ramp circuit
42
becomes sequentially larger each time the timing signal Stm is output from the comparator circuit
43
, the time at which the output of the fast ramp circuit
41
and the output of the slow ramp circuit
42
agree is delayed by only time T5 from the rise of the trigger signal Str. Similarly, each time the trigger signal Str is input, the rise is delayed as shown by T6 and T7. By this operation, timing for the sampling of a measured signal is obtained by changing the time elapsed from the trigger signal Str.
In this connection, in the EOS oscilloscope shown in FIG.
3
and
FIG. 4
, since the output of the slow ramp circuit
42
is obtained by a D/A conversion circuit
42
b
, during the operation of the D/A conversion the output of the slow ramp circuit
42
becomes unstable (the section shown by reference number S
1
in FIG.
2
(
c
)), and as a result the output of the comparator circuit
43
also becomes unstable (the section shown by reference number S
2
in FIG.
2
(
d
)). In addition, because the output of the fast ramp circuit
41
is a ramp wave, a certain period of time after becoming the maximum value, the operation for returning to the minimum value is repeated. Therefore, at the point in time of returning to the minimum value from the maximum value, an unnecessary signal (the section shown by reference number S
3
in FIG.
2
(
d
)) is output form the comparator circuit
43
because there is a timing that agrees with the output of the slow ramp circuit
42
. Because the output of the comparator circuit
43
is the timing signal Stm, when unstable signals and unnecessary signals are output, there is the problem that accurate sampling cannot be carried out.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide an EOS oscilloscope that can prevent the output of an unstable output value from the comparator circuit, and can improve the precision of the timing signal.
According to the present invention, this objective can be attained by an electro-optical sampling oscilloscope apparatus that carries out measurement of measured signal by using an optical pulse generated based on a timing signal generated from a timing generation circuit synchronous with a trigger signal, providing the timing generation circuit comprising a fast ramp circuit that outputs a ramp waveform using said trigger signal as a trigger; a slow ramp circuit that increases stepwise and sequentially the output value according to said timing signal; a comparator circuit that compares the output of said fast ramp circuit and the output of said slow ramp circuit and outputs the results of this comparison; and a gate circuit that limits the output of said comparator circuit by closing a gate only when the output of said comparator circuit is unstable based on the input trigger signal and timing signal.
In addition, the present invention provides the advantages that the precision of the timing signal is improved because unnecessary

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