Timing generation circuit and method for timing generation

Details Timing generation circuit and method for timing generation Timing generation circuit and method for timing generation

2000-02-09

2003-06-03

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S158000, C327S161000

Reexamination Certificate

active

06573776

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing generation circuit for adjusting the timing of a clock signal used in a semiconductor integrated circuit. In particular, the present invention relates to a timing generation circuit incorporating a DLL (delayed logic loop) and a method for timing generation.
2. Description of the Related Art
A conventional timing generation circuit incorporating a DLL may be constructed as shown in
FIG. 8
, for example. With reference to
FIG. 8
, when an input buffer
101
receives a clock signal CLK at its input, the input buffer
101
generates a signal A by delaying the clock signal CLK by a delay time d
1
, and the signal A is output to a timing compensation section
102
. The timing compensation section
102
further delays the signal A by an appropriate amount of time, and transfers the resultant signal to an output buffer
103
. The output buffer
103
further delays the signal A by a delay time d
2
, and outputs a clock signal ICLK. As a result, the output clock signal ICLK is delayed by one cycle relative to the input clock signal CLK, so that both clock signal CLK and ICLK synchronize with each other, as described below in more detail.
The timing compensation section
102
is employed for the following reason. If the timing compensation section
102
is omitted, so that the clock signal CLK is input to the input buffer
101
and the clock signal ICLK is output from the output buffer
103
, then the clock signal ICLK will lag behind the clock signal CLK by a sum of delay times d
1
+d
2
, so that the clock signal CLK and the clock signal ICLK are no longer in synchronization with each other. Accordingly, the timing compensation section
102
is employed to ensure that the sum of delay times d
1
+d
2
apparently equals zero.
The timing compensation section
102
includes a delay circuit
111
, an upper delay line
112
having a plurality of upper delay circuits
112
-
0
to
112
-
7
, and a lower delay line
113
having a plurality of lower delay circuits
113
-
0
to
113
-
7
. The delay circuit
111
, the upper delay line
112
, and the lower delay line
113
together compose a DLL (delayed logic loop).
The delay circuit
111
receives the signal A, which has been delayed in the input buffer
101
by the delay time d
1
relative to the clock signal CLK. The delay circuit
111
further delays the signal A by a delay time which is equal to d
1
+d
2
so as to generate a signal B, which in turn is applied to the upper delay line
112
. Each of the upper delay circuits
112
-
0
to
112
-
7
of the upper delay line
112
, all of which have the same compensatory delay time, delays the signal B by its respective compensatory delay time as the signal B is transferred downstream.
The lower delay circuits
113
-
0
to
113
-
7
of the lower delay line
113
have the same compensatory delay time as that of the upper delay circuits
112
-
0
to
112
-
7
of the upper delay line
112
. Upon receiving the signal A, each of the lower delay circuits
113
-
0
to
113
-
7
of the lower delay line
113
delays the signal A by its respective compensatory delay time as the signal A is transferred downstream.
When the signal A which is output from the input buffer
101
comes to a next rising edge, the signal B rises in one of the upper delay circuits
112
-
0
to
112
-
7
of the upper delay line
112
. In response to this, one of signals a, b, c, d, e, f, g, and h is output to a corresponding one of the lower delay circuits
113
-
0
to
113
-
7
of the lower delay line
113
. Further in response thereto, the corresponding one of the lower delay circuits
113
-
0
to
113
-
7
of the lower delay line
113
outputs the signal A to the output buffer
103
.
The operation of the above-described timing generation circuit will now be described with reference to a timing chart shown in FIG.
9
.
The delay time from a rising edge of the signal A to a rising edge of the signal B is equal to d
1
+d
2
, i.e., the delay time applied by the delay circuit
111
.
Assuming that one cycle of the clock signal CLK is Tck, the delay time from a rising edge of the signal B to the next rising edge of the signal A is equal to Tck−(d
1
+d
2
).
After the rising edge of the signal B is received by the upper delay line
112
, the signal B may rise in, e.g., the upper delay circuit
112
-
3
of the upper delay line
112
responsive to the next rising edge of the signal A. In this case, the signal d is output from the upper delay circuit
112
-
3
and applied to the lower delay circuit
113
-
3
of the lower delay line
113
. As a result, the signal A is output from the lower delay circuit
113
-
3
.
During the aforementioned process, the rising edge of the signal B is delayed by the upper delay circuits
112
-
0
to
112
-
3
of the upper delay line
112
until the next rising edge of the signal A. Therefore, the rising edge of the signal B has been delayed by a delay time which is equal to Tck−(d
1
+d
2
). The lower delay circuit
113
-
0
to
113
-
3
of the lower delay line
113
, which essentially has the same structure as the upper delay line
112
, also apply a delay time which is equal to Tck−(d
1
+d
2
). Accordingly, the signal A from the input buffer
101
will have been delayed in the lower delay circuits
113
-
0
to
113
-
3
of the lower delay line
113
by the delay time Tck−(d
1
+d
2
) before being applied to the output buffer
103
.
Accordingly, the total delay time from the input buffer
101
to the output buffer
103
is equal to d
1
+Tck−(d
1
+d
2
)+d
2
=Tck. In other words, the clock signal CLK which is input to the input buffer
101
is delayed by one complete cycle Tck of the clock signal CLK before being output from the output buffer
103
as the clock signal ICLK. Thus, the clock signal CLK which is input to the input buffer
101
and the clock signal ICLK which is output from the output buffer
103
are synchronized with each other.
By adjusting the delay time (d
1
+d
2
) between the signals A and B, it is also possible to prescribe a negative delay time. For example, if a delay time (d
1
+d
2
−d
3
) is set in the delay circuit
111
instead of (d
1
+d
2
), the clock signal ICLK which is output from the output buffer
103
will have been delayed by a delay time−d
3
(see Japanese Laid-Open Patent Publication No. 9-121147).
In another conventional example illustrated in
FIG. 18
, a variable delay subsection
123
is inserted between an input circuit
121
and an output circuit
122
. A phase comparator circuit
124
adjusts the delay time in the variable delay subsection
123
so as to maintain synchronization between a clock signal CLK which is input to the input circuit
121
and a clock signal ICLK which is output from the output circuit
122
. Specifically, the phase comparator circuit
124
adjusts the delay time in the variable delay subsection
123
so that a signal A from the input circuit
121
, which has been delayed by a delay time d
1
, stays in synchronization with a signal B from a dummy input circuit
125
which has also been delayed by d
1
. As a result, the variable delay subsection
123
outputs a signal C, which is delayed by a delay time −d
2
, to the output circuit
122
. The signal C is output from the output circuit
122
as the clock signal ICLK.
In the aforementioned conventional timing generation circuit shown in
FIG. 8
, the delay time in the upper delay circuits
112
-
0
to
112
-
7
of the upper delay line
112
and the lower delay circuits
113
-
0
to
113
-
7
of the lower delay line
113
defines the minimum unit delay time which allows for adjustment. As this unit delay time is decreased, the synchronization between the respective clock signals can be adjusted with a higher accuracy. For example, if the unit delay time in the respective upper delay circuits
112
-
0
to
112
-
7
and the respective lower delay circuits
113
-
0
to
113
-
7
is 1 ns,

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