Timing generating circuit and method

Details Timing generating circuit and method Timing generating circuit and method

1996-09-20

1999-05-04

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327231, 327236, 327237, 327276, 327105, 327164, H03K 513, H03K 5159

Patent

active

059007613

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a circuit for generating a timing signal and a method of generating a timing signal, which are applied, for example, to a semiconductor device testing apparatus and can generate a signal at a preset timing, and particularly, to such circuit and method which can generate a stable timing signal even in variation of temperature.


BACKGROUND OF THE RELATED ART

Electronic circuits each having a gate array formed by CMOS (complementary metal-oxide semiconductor) structure FETs (field effect transistors) tend to increase signal transmission delays as the temperature increases. It was thus necessary, when integrating a high precision timing generator formed by CMOS.FETs into an LSI, to incorporate therein a function that would always compensate for the variations in signal transmission delays resulting from the temperature variations. Especially, in the LSI formed by CMOS.FETs, the signal transmission delays not only may vary with the temperature variation in the LSI chip based on the ambient temperature changes but also based on the generation of heat in the LSI chip itself due to the transition between a high level and a low level of a signal that propagates through the CMOS.FETs. Therefore, the more frequently the edge transitions of a digital data occur that propagates through the CMOS.FETs, the higher the temperature in the LSI chip rises.
A timing generating circuit is arranged such that it receives a timing pulse consisting of a series of impulses or pulses inputted thereto, passes it through a delay element or elements the delay times of which are settable, and outputs a timing pulse with the set delay amount (phase). However, if the timing generating circuit is formed into a CMOS.LSI, the temperature of the CMOS cell itself (a basic gate unit formed by CMOS.FETs in the LSI) may vary between immediately before and after the timing generating circuit is activated. For example, when a timing pulse 11 is inputted to the CMOS cell at time t.sub.0 as shown in FIG. 1A, the temperature thereof goes up step by step for each impulse of the input timing pulse 11 and then goes down very slowly, as shown in the curve 12 in FIG. 1B, and repeats such cycle, resulting in an overall increase in the cell temperature. With this temperature increase, the delay amount of the output timing pulse increases from the set value, as shown in the curve 13 in FIG. 1C, in a similar manner to the temperature increase curve 12, resulting in a degradation in the precision of timing. Therefore, in a timing generator for an application requiring a timing with high accuracy, it was required that various timing generating circuits of the timing generator have means for compensating for cell temperature variations independently provided, respectively.
When a timing pulse is received intermittently, i.e., in groups of impulses as shown in FIG. 1D, a deviation or lag of the output timing from the set value is increased for each group of pulses and is decreased between the groups of pulses as shown in FIG. 1E, which results in generation of so-called heat jitters.
To solve such a problem in a conventional high precision timing generator circuits, it was customary to always maintain the consumed electric power constant. That is, this problem was addressed by providing a dummy delay element of the same cell adjacent to a delay element such that the sum of the consumed electric power (generated heat amount) in both delay elements becomes a constant amount by causing the input timing pulse to pass through this dummy delay element when no timing pulse is outputted. This solution, however, could not remove most of the heat jitters caused by temperature variations that could occur faster than the heat propagation time delay from the dummy delay element, since the heat propagation time delay was caused due to distances between the adjacent cells. It was also difficult to perform stable temperature compensation due to potential changes in the heat generating conditions from the surrounding cells

REFERENCES:
patent: 4504749 (1985-03-01), Joshida

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