Timing driven method for laying out a user's circuit onto a prog

Details Timing driven method for laying out a user's circuit onto a prog Timing driven method for laying out a user's circuit onto a prog

1995-01-19

1996-05-28

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, 364490, G06F 1750

Patent

active

055218377

ABSTRACT:
The present invention provides suggested delay limits for use by layout tools which cause a programmable integrated circuit device to implement a logic design. The suggested delay limits can be used by such tools as an initial placement algorithm, a placement improvement algorithm, and a routing algorithm for evaluating and guiding potential layouts. The suggested delay limits take into account characteristics of the programmable device being used by estimating lower bound delays for each connection in a logic design, and take into account any previously achieved delays or achievable delays for each connection in calculating the suggested limits. Results of routing benchmark designs using the novel suggested limits show improved timing performance for all benchmark cases tested.

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