Timing-driven integrated circuit layout through device sizing

Details Timing-driven integrated circuit layout through device sizing Timing-driven integrated circuit layout through device sizing

1995-07-11

1997-08-05

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, 364491, G06F 1750

Patent

active

056548982

ABSTRACT:
A method and apparatus for determining the layout of an integrated circuit, in accordance with timing constraints, by means of sizing the buffers in the layout. A nominal netlist for the layout of the integrated circuit is used to determine critical paths through the circuit. The time-critical paths are determined and the instances of the buffers along the path are resized so that the time delays in the time-critical paths are either brought within the predetermined timing criteria, or no further improvement in any time-critical path is possible.

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