Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2001-05-24
2003-04-08
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S408000, C327S119000
Reexamination Certificate
active
06545518
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a signal controlling method and apparatus.
BACKGROUND OF THE INVENTION
A conventional signal dividing method for dividing (internally dividing or interpolating) a timing difference is used for multiplying the frequency of clock signals, as disclosed in Publication 1 (Japanese patent application 09-157028 (JP Patent Kokai JP-A-11-4145)).
In e.g., Publication 2 (ISSCC Digest of Technical Papers pp.216 to 217, February 1996, U.S. Pat. Nos. 5,442,835 and 5,530,837), there is disclosed a clock signal frequency multiplying circuit, as shown herein in FIG.
24
.
Referring to
FIG. 24
, the clock signal frequency multiplying circuit is made up of four sets of delay circuits
301
to
304
, a phase comparator
309
and a counter
310
, in case of 4× frequency multiplying.
Each of the first to fourth delay circuits
301
to
304
has its output terminals selected by first to fourth switchers
305
to
308
, with the first to fourth delay circuits
301
to
304
being connected in series with one another.
A first clock
311
, input from outside to the first delay circuit
301
, is compared in the phase comparator
309
with a fifth clock
315
passed through the first to fourth delay circuits
301
to
304
. An UP signal
316
or a DOWN signal
317
is transferred to the counter
310
, based on the results of comparison, and a control signal
318
is output from the counter
310
to the first to fourth switchers
305
to
308
to make adjustment so that the first clock
311
will be of the same phase (in-phase) to the fifth clock
315
.
Since the four delay circuits
301
to
304
are adjusted equally in delay time, the delay time is equal, with the timing difference of the first to fourth clocks
311
to
314
being equal to one another at one-fourth of the clock period tCK.
Thus, by synthesising the first to fourth clocks
311
to
314
, 4× clocks are produced.
As a circuit for multiplying the frequency of clock signals, a phase locked loop (PLL) is used. In the PLL, shown in
FIG. 25
, an output of a voltage-controlled oscillator VCO
322
is frequency-divided by a frequency divider
323
, and the resulting signal is compared by a phase comparator
319
to an external clock
324
. The result of comparison is input as an UP signal
325
or a DOWN signal
326
via a charging pump
320
and a loop filter
321
to the VCO
322
to control the VCO
322
so that clocks obtained on frequency-dividing the output of the VCO
322
will be of a frequency equal to a frequency of the external clock
324
. This causes the VCO
322
to output frequency-multiplied clocks
327
with the number of times of multiplying equal to a reciprocal of the number of times of frequency division.
However, the circuit shown in
FIG. 24
is such a circuit comparing a signal which has traversed the series-connected delay circuits to external clocks approximately several tens of times to correct the delay difference and the phase difference progressively as comparison proceeds.
On the other hand, the PLL circuit, shown in
FIG. 25
, has a drawback that it is insufficient in operating speed, since clocks obtained on frequency division of the output of the VCO
322
will be of a frequency equal to the frequency of the external clock
324
, such that a time interval not less than several tens of clock periods must elapse until the clocks multiplied in frequency are obtained.
The circuits shown in
FIGS. 24 and 25
basically can be used only for clock control, while it cannot be used as a delay circuit for varying the degree of signal delay.
With a view to solving these drawbacks and to realizing a method and apparatus for controlling the clock signals also usable as a variable delay circuit, the present inventors have proposed the following circuit configuration in the JP-A-11-4145. The clock control circuit, described in JP-A-11-4145, is now explained by referring to the drawings, the entire disclosure of which is herein incorporated by reference thereto.
FIG. 4
shows the configuration of the JP-A-11-4145. The circuit shown in
FIG. 4
multiplies the frequency of external clocks. Specifically, the circuit shown in
FIG. 4
frequency divides external clocks
1
into multi-phase clocks
3
and divides the input timing difference of different phase pulse edges of the multi-phase clocks
3
or multiplexes the clocks
9
c
of different phases resulting from the division to multiply the phases of the external clock
1
. The circuit shown in
FIG. 4
includes a frequency divider
2
, a multi-phase clock frequency multiplying circuit
5
and a clock synthesis circuit
8
. The frequency divider
2
divides the frequency of the external clock
1
to the multi-phase clocks
3
. A multi-phase clock multiplying circuit
5
includes a timing difference dividing circuit
4
a
for dividing pulses of different phases of different phase clocks of the multi-phase clocks
3
, timing difference dividing circuits
4
a
for dividing the pulses of the same phase by n and a multiplying circuit
4
b
for multiplying different phase pulses resulting from division by n, and outputs multi-phase clocks
9
a.
The clock synthesis circuit
8
synthesises the multi-phase clocks
9
a
, output from the multiplying circuit
4
b
, to generate single-phase clocks
9
. The timing difference dividing circuits
4
a
are connected in parallel with one another.
The external clocks
1
are frequency divided by the frequency divider
2
into the multi-phase clocks
3
, and the input timing difference of different phase pulse edges of the frequency divided multi-phase clocks
3
is divided by a timing difference dividing circuit
4
a
. The resulting clocks
9
c
of different phases, obtained on frequency division, are multiplexed to multiply the external clock
1
, to multiply the phases of the multi-phase clocks.
FIG. 5
shows an illustrative structure of a two-phase clock multiplying circuit as the multi-phase clock frequency multiplying circuit
5
. The two-phase clock multiplying circuit divides the frequency of the external clocks
105
by two to output two-phase clocks having the double (2×) frequency.
In
FIG. 5
, a frequency divider
101
divides the frequency of the external clocks
105
by two to generate two-phase clocks D
1
, D
2
. Plural two-phase clock multiplying circuits
102
1
to
102
n
divide the input timing difference of different phase pulse edges of the frequency divided multi-phase clocks D
1
, D
2
(
3
of FIG.
4
), the first stage two-phase clock multiplying circuit
102
1
generates two-phase clock signals D
11
, D
12
obtained on frequency doubling the two-phase clocks D
1
, D
2
from the frequency divider
101
. In similar manner, the two-phase clock multiplying circuits
102
1
,
102
3
to
102
n−1
each doubles the frequency of the clocks D
21
, D
22
of the previous stage so that two-phase clocks Dn
1
, Dn
2
obtained on 2nX-multiplying the external clocks
105
are obtained by the two phase clock multiplying circuit
102
n
of the last stage.
A clock synthesis circuit
103
synthesises 2nX-multiplied two-phase clocks Dn
1
, Dn
2
output from the last stage two phase clock multiplying circuit
102
n
to output multiplied clocks
107
.
A period detection circuit
104
(
6
of
FIG. 4
) is fed as an input with the external clocks
105
to output a control signal
106
(
7
of
FIG. 4
) to each two-phase clock multiplying circuits
102
1
to
102
n
. The control signal
106
corrects the clock period dependency of the timing difference dividing circuit contained in each two-phase clock multiplying circuits
102
1
to
102
n
for load adjustment.
The period detection circuit
104
is made up of a ring oscillator of a fixed number of stages and counters and counts the number of oscillations of the ring oscillators during the period of the external clocks
105
to output a control signal
105
depending on the number of counts.
The two-phase clock multiplying circuits
102
1
to
102
n
are freed of fluctuations in characteristics by the control signal
106
from t
Hayes & Soloway P.C.
Le Dinh T.
NEC Electronics Corporation
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