Timing diagram method for inputting logic design parameters to b

Details Timing diagram method for inputting logic design parameters to b Timing diagram method for inputting logic design parameters to b

1995-09-25

1998-04-28

Teska, Kevin J.

Boots, shoes, and leggings

364490, G06F 1562

Patent

active

057453861

ABSTRACT:
A. system (i.e. a tool set) provides logic verification at the logic design level in which an external stimulus to the design is derived from a series of generalized timing diagrams that obey the interface protocols of the logic design under test. A timing diagram editor provides a graphical user interface that allows the logic designer to describe his or her logic in a general timing diagram format incorporating permutations of the interface specification. The output of the timing diagram editor is a file that describes the interfaces of the logic; this file can contain multiple timing diagrams that describe different interface interactions. A suitable simulation driver reads the file created by the timing diagram editor, learns the interfaces described therein, and uses simulation randomization algorithms to drive the interfaces with legal scenarios for the interfaces described in the timing diagram.

REFERENCES:
patent: 4364036 (1982-12-01), Shimizu
patent: 4554536 (1985-11-01), Jackson
patent: 4914568 (1990-04-01), Kodosky
patent: 5073853 (1991-12-01), Johnson
patent: 5173869 (1992-12-01), Sakamoto
patent: 5187677 (1993-02-01), Kovalick
patent: 5210837 (1993-05-01), Wiecek
patent: 5313615 (1994-05-01), Newman
patent: 5371851 (1994-12-01), Pieper
patent: 5375125 (1994-12-01), Oshimitsu
patent: 5381524 (1995-01-01), Lewis et al.
patent: 5384720 (1995-01-01), Ku
patent: 5623418 (1997-04-01), Rostoker et al.

Affiliated with

Also associated with

Rating

Timing diagram method for inputting logic design parameters to b does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing diagram method for inputting logic design parameters to b, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing diagram method for inputting logic design parameters to b will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1539085