Timing device and timing method

Details Timing device and timing method Timing device and timing method

2000-11-13

2003-09-16

Vo, Huy D. (Department: 2665)

Multiplex communications

Communication over free space

Having a plurality of contiguous regions served by...

C370S347000, C370S509000, C375S354000, C375S365000

Reexamination Certificate

active

06621806

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a timing device and a timing method as well as to an application of the timing device.
U.S. Pat. No. 5,594,737 teaches a configuration for controlling a transceiver of a base station and/or mobile units of a mobile radio system. A processor is provided therein which is equipped with a timer, i.e. a counter, and with the aid of which controls other elements of the system such as the transceiver. This type of control is necessary in mobile radio systems based on TDMA, because the mobile unit transmits in one time slot and receives in another in alternation. The time sequence and duration of the transmission and reception time periods are stipulated in the respective mobile radio standard, e.g. GSM or DECT. The time points or periods can vary within defined limits over the duration of a communication.
Among other things, the control processor in U.S. Pat. No. 5,594,737 generates timing signals for the other circuit parts so that these can be activated and deactivated at the required times. A typical example of this is the antenna switch, which connects the antenna to the reception path or the transmission path as required. Whereas U.S. Pat. No. 5,594,737 demonstrates a configuration that can be used for the DECT mobile radio standard in particular, WO 98/13949 demonstrates a similar structure to that of the invention that can be used for the GSM mobile radio standard in particular. The logic and control block LSB therein takes over the function, among others, of switching the circuit parts of a TDMA reception device in and out as required.
FIG. 5
shows the essential elements of the timing device which is used in a module of the applicant, which is available under the model number PMB 2800. According to
FIG. 5
, the instantaneous count of a TDMA clock counter that is 15 bits wide is delivered to a plurality of comparison units COMPARE
1
, COMPARE
2
, . . . . The TDMA clock counter is controlled by a cycle with a frequency of 2.166 MHz. Each TDMA comparison unit compares the instantaneous count of the TDMA clock counter to a set value, e.g. SET 1, and a reset value, e.g. RST 1. When the instantaneous count of the TDMA clock counter matches the set value, the comparison unit sets its appertaining output signal, e.g. S
1
. The output signal remains set until the TDMA clock counter attains the reset value—i.e., the instantaneous counter status matches the reset value—whereupon the comparison unit resets the output signal. The set value and the reset value for each of the output signals S
1
, S
2
, . . . are deposited in respective registers SET1 and RST1, whose contents are defined by a control device &mgr;C.
With the aid of a circuit as represented in
FIG. 5
, it is possible to generate signal characteristics as represented in FIG.
6
. For instance, the signal S
1
is active in the region of the reception slot
0
, whereas the output signals S
9
and S
10
are active in the region of the transmission slot
3
. Other signals serve to actuate circuit parts which relate to the transmission and reception or to the monitoring of a monitor channel in the time slot
5
. The time position of the TDMA frames and the allocation of transmission, reception and monitoring time slots are defined by the base station of the mobile radio system. The mobile unit—in which the module PMB 2800 is preferably employed—has to adapt the time indications that are required for transmission, reception or monitoring to the specifications of the base station and to the situation of the radio transmission path at the moment. The time indications that are provided for the mobile part must be adjusted relative to the TDMA frame depending on whether the mobile unit is moving away from the base station or toward it, in order to compensate shorter or longer radio communication transit times, accordingly. This is represented in
FIG. 6
by corresponding black blocks in the individual signals, which represent the permitted time window for a signal change. Similarly, the time indications must be adapted to the requirements of a respective circuit environment (in the context of a chip set). The control unit &mgr;C that is represented in
FIG. 5
can set the required signal change times by programming the set and reset registers accordingly.
A disadvantage of the previous configuration is that for each of the signals S
1
, S
2
. . . S
10
in
FIG. 6
precisely one comparison unit COMPARE
1
, COMPARE
2
, . . . must be provided, which generates the respective signal at its output. If the module that contains this circuit is used in an environment that requires a higher number of time signaling operations, the module cannot provide them. Furthermore, the time indications of different signals are partly dependent on one another. This is either accounted for by a fixed wiring between the set and reset inputs at the comparison units, or alternatively the control unit &mgr;C programs the set and reset registers in a corresponding manner. But a fixed wiring suffers from a lack of flexibility of the signal generation process. The alternative procedure consumes computing power of the control unit &mgr;C, which should be loaded as little as possible by the reprogramming of the set and reset registers, since it must manage several other tasks in its circuit environment. Current requirements of the aforementioned mobile radio standards, particularly GSM (see e.g. ETSI prETS
300
908
, November 96 for multislot applications) require a far greater number of timing signals than hitherto, which must be mutually adjustable in a flexible manner.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a timing device and a timing method which overcomes the above-mentioned disadvantageous of the prior art devices and methods of this general type such that a plurality of timing signals can be generated in a flexible fashion.
With the foregoing and other objects in view there is provided, in accordance with the invention a timing device for generating and outputting a plurality of signal edges by changing signal statuses at predeterminable times. It includes a cyclically addressed memory in which a plurality of time events are stored. Each time event is assigned a time value and a plurality of signal statuses. The time value corresponds to a predetermined time point. The timing device further includes a comparator that compares the instantaneous count of a counter to the time value, which has just been read from the memory, of a time event, and which reads the next time event from the memory given a match. The timing device also includes an output device, which outputs the predetermined signal statuses. It is thus possible to flexibly generate a plurality of timing signals by allocating memory accordingly. The number of time events and the number of timing signals per time event can be designed with complete flexibility, limited only by the available storage space. Furthermore, it is also possible to effortlessly achieve more than one set and reset process per count cycle for a timing signal, because this can also be accomplished by a simple allocation of memory. In particular, simultaneous time indications can be achieved on different timing signals by the corresponding allocation of memory, and need not be generated by a hard-wired logical connection between the timing signals as was done previously.
In accordance with an added feature of the invention, the timing device includes a time shift mechanism, which is connected in series with the comparator. The time shift mechanism adds a time shift value to the time value that is read from the memory. The result of the addition is then fed to the comparator. To this end, the time shift mechanism preferably includes a register in which the time shift value is stored. The time shift value can assume both positive and negative values. As long as a value other than zero is stored in the register of the time shift mechanism, the time indications that are generated therefrom either precede or fo

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