Timing delay modulation scheme for integrated circuits

Details Timing delay modulation scheme for integrated circuits Timing delay modulation scheme for integrated circuits

1995-06-23

1996-08-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327172, 327 77, H03K 513, H03K 5153

Patent

active

055505007

ABSTRACT:
A timing delay modulation scheme for integrated circuits (10) is disclosed. A super voltage is applied to existing bond pads (30) and detected by super voltage detect circuits (34) which generate a number of logic input signals (22) to a logic unit (18). In response, the logic unit (18) provides a number of control signals (24) which are coupled to timing adjust circuits (20). In the preferred embodiment, in response to its respective control signals, each timing adjust circuit (20) pushes-out or pulls-in, a separate internal timing signal (S0-S3) of the integrated circuit. The super voltage detect circuit (34) includes an adjustable effective super voltage level, and is capable of being disabled. Further, the timing adjustment provided by each timing adjust circuit (20) can be altered.

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patent: 5440260 (1995-08-01), Hayashi et al.
patent: 5446321 (1995-08-01), Yoshino et al.

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