Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2006-08-11
2009-12-15
Cox, Cassandra (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S276000
Reexamination Certificate
active
07633326
ABSTRACT:
A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.
REFERENCES:
patent: 4719608 (1988-01-01), Genat et al.
patent: 4859954 (1989-08-01), Yoshimura
patent: 4999526 (1991-03-01), Dudley
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5179303 (1993-01-01), Searles et al.
patent: 5204564 (1993-04-01), Ochiai
patent: 5216302 (1993-06-01), Tanizawa
patent: 5223755 (1993-06-01), Richley
patent: 5245231 (1993-09-01), Kocis et al.
patent: 5304953 (1994-04-01), Heim et al.
patent: 5355037 (1994-10-01), Andresen et al.
patent: 5376849 (1994-12-01), Dickol et al.
patent: 6075395 (2000-06-01), Saeki
patent: 6229363 (2001-05-01), Eto et al.
patent: RE37232 (2001-06-01), Saeki
patent: 6313674 (2001-11-01), Akita et al.
patent: 0-460-669 (1991-12-01), None
patent: 55-166331 (1980-12-01), None
patent: 3-241918 (1991-10-01), None
patent: 4-364609 (1992-12-01), None
patent: 6-112782 (1994-04-01), None
patent: 6-232709 (1994-08-01), None
patent: 09215005 (1997-08-01), None
W. Jutzi: “Active Tapped Delay Line Filter,” IBM Technical Disclosure Bulletin, vol. 12, No. 9, Feb. 1970.
Timo Rahkonen et al.: “The Use of Stabilized CMOS Delay Lines in the Digitization of Short Time Intervals,” IEEE International Symposium on Jun. 16, 1991, vol. 4, pp. 2252-2255.
Cox Cassandra
Fujitsu Microelectronics Limited
Kratz Quintos & Hanson, LLP
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