Timing controller and controlled delay circuit for...

Details Timing controller and controlled delay circuit for... Timing controller and controlled delay circuit for...

2000-03-03

2001-12-25

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S284000

Reexamination Certificate

active

06333657

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing controller and a delay circuit (controlled delay circuit), and more particularly, to a timing controller adopted for electronic circuits, for controlling the timing of a signal by changing the phase of the signal.
2. Description of the Related Art
Recent computers employ high-speed CPUs (central processing units: MPUs) and electronic circuits. These high-speed devices require high-speed interfaces.
The access time of a synchronous memory (for example, synchronous dynamic random access memory: SDRAM) is basically determined by a delay time in an input buffer, a delay time in long wiring, and a delay time in an output buffer. These delay times are reducible only by reducing the chip size or by improving the transistor characteristics. It is very difficult, therefore, to provide high-speed synchronous memories.
LSI chips are becoming larger, and the delay time in the long wiring reaches one nanosecond or more. These are many LSIs that have an access time of five nanoseconds or longer. The long access time limits the rate of continuous access operations to about 100 MHz.
On the other hand, the signal frequency inside a chip can be increased by employing a pipeline structure and parallel-serial conversion. An output circuit of the chip, however, is incapable of following the internal speed of the chip. It is required, therefore, to provide a timing controller for properly controlling the timing of a control signal to the output circuit according to the period of the control signal. The problems of the prior art will be explained hereinafter in detail with reference to the accompanying drawings.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a timing controller for properly controlling the timing of a control signal according to the period of the control signal. Further, another object of the present invention is to provide a controlled delay circuit for obtaining a signal including a required delay time or a required frequency by decreasing consumption power without receiving influence of noises caused by power voltage or temperature fluctuations. In addition, still another object of the present invention is to provide a controlled delay circuit (control signal generator) capable of correctly generating a high-speed clock signal without a quantization error or an offset, as well as providing a controlled delay circuit used for such a control signal generator.
According to the present invention, there is provided a controlled delay circuit comprising a first gate chain for measuring a time difference between a changeover point of a first control signal and a changeover point of a second control signal; and a second gate chain, receiving third signals which are generated in the first gate chain and represent the time difference, for providing an appropriate delay time from an input to an output depending on the time difference.
The third control signal may be stored in a memory or a register circuit to fix the third control signal. The data stored in the memory or register circuit may be renewed in accordance with specific clock cycles.
Further, according to the present invention, there is provided a controlled delay circuit comprising a first gate chain having gate circuits connected in series to transmit a signal in a first direction; a second gate chain having gate circuits connected in series to transmit a signal in a second direction opposite to the first direction; and a control circuit for activating and inactivating at least a part of the first gate chain according to a first control signal and at least a part of the second gate chain according to a second control signal, and at least one node in the first gate chain being short-circuited to at least one node in the second gate chain, to invert an input signal to the first gate chain and provide an output signal from the second gate chain.
A number of the gate circuits in the first gate chain may be at least three and be equal to or greater than a number of the gate circuits in the second gate chain. The first and second control signals may be produced according to a common signal, which may be set to a first level to activate the first gate chain and inactivate the second gate chain and to a second level to inactivate the first gate chain and activate the second gate chain. The control circuit may produce the first and second control signals according to a clock signal and a general control signal for controlling the controlled delay circuit as a whole.
The control circuit may contain a frequency divider. The control circuit may divide a frequency of an input signal to the first gate chain by N (N being an integer equal to or greater than two), to produce control signals each having a period that is N times as long as a period of the input signal, supply the control signals to N sets of the first and second gate chains, and superpose outputs of the N sets, to provide an output signal having the same frequency as and a different phase from the input signal. The control circuit may halve the frequency of the input signal to the first gate chain, to produce complementary control signals each having a period twice as long as that of the input signal, supply the first control signal and second control signal to two sets of the first and second gate chains, and superpose outputs of the two sets, to provide an output signal having the same frequency as and a different phase from the input signal.
The first control signal and second control signal may be supplied to the gate circuits of the first gate chain and second gate chain through respective signal lines. The signal lines may be connected to the gate circuits of the first gate chain and second gate chain through buffers arranged for every predetermined number of the gate circuits. The buffers may be inverters through which the signal lines are alternately connected to the first and second gate chains.
Sizes of transistors forming the gate circuits of the first gate chain may be differentiate from sizes of transistors forming the gate circuits of the second gate chain, to temporally multiply the delay time generated in the first gate chain by a given value, which may correspond to a ratio of the transistor sizes, and invert the multiplied input signal. Each of the gate circuits of the first and second gate chains may be an inverter having a power source controlling transistor to be switched in response to a control signal, to activate one of the first and second gate chains.
Each of the gate circuits of the first and second gate chains may be an inverter, a level of a voltage applied to the inverters being changed to activate one of the first and second gate chains. Each common node in the first and second gate chains may be provided with a capacitor element to control signal propagation delay characteristics of the gate circuits. Capacitances of the capacitor element may be gradually increased from an input side of the first gate chain toward an output side thereof.
An output end of the first gate chain may be set to a high impedance state, an input end of the second gate chain may be fixed at first potential, an input signal of second potential supplied when the first gate chain is activated may be reversely transmitted when the second gate chain is activated, so that data of the first potential appears at an output end of the second gate chain, to thereby reproducing a time difference between a changeover point of the input signal to the first gate chain and a changeover point of the first control signal by a time difference between a changeover point of the second control signal and a changeover point of the output of the second gate chain.
An input end of the first gate chain may be provided with a one-way drive circuit for driving the first gate chain only to one of the first potential and second potential. An output end of the second gate chain may be provided with an output buffer for catching only a changeover point from first potential to second

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