Timing control method in a common bus system having delay and ph

Details Timing control method in a common bus system having delay and ph Timing control method in a common bus system having delay and ph

1990-01-10

1992-06-16

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642383, 3642401, 364242, 364271, 3642715, 3649402, 3649503, 3649504, 3408252, 34082514, 370 851, G06F 1336, G06F 1342

Patent

active

051231000

ABSTRACT:
In a common bus control method, transmission and reception buses are connected to a unit having a unit number 1. A synchronization frame head signal for time-division slots of common buses is sequentially supplied to the units in the order of the unit numbers 1 to n through delay circuits. Phase correcting circuits are respectively connected to the transmission and reception buses of each unit so as to perform phase correction of data on the buses and latch signals for latching the data. The delay circuit arranged in each unit sets transmission delay data having an inherent delay difference on the basis of the synchronization frame head signal. An output from the delay circuit of each unit is used as the latch signal.

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