Timing control means for automatic compensation of timing...

Details Timing control means for automatic compensation of timing... Timing control means for automatic compensation of timing...

2001-07-03

2004-12-21

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Measurement system

Statistical measurement

C702S125000, C702S176000, C702S179000, C702S089000, C326S093000

Reexamination Certificate

active

06834255

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OF DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the reducing of timing uncertainties in high-performance multiple channel devices. More specifically, the present invention relates to a device and method for minimizing timing uncertainties due to asymmetry of rising and falling edges and also duty cycle inaccuracy. The invention can be employed in a digital interface between two items or within a circuit where there is a requirement for tight timing control such as requirement for a low skew between the channels of a register.
The present invention is particularly applicable to digital systems of data transmission, interfaces to memory devices, to test equipment for testing semiconductor devices and to high-speed communications, especially for systems with double data transmission rate (DDR).
2. Description of the Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
Transistor linewidths have been reducing according to Moore's Law since around 1971: this involves a doubling of the density of transistors every 18 months. The speed of a transistor, such as a MOSFET, is proportional to the inverse of the square of the channel length, which means that many integrated circuits are now able to operate at speeds above 1 GHz internally. Except for a small number of extremely complicated interfaces, or for serial interfaces, the interface speeds have been a small fraction of the maximum chip operating speed. Another problem has been the width of the interface: the problem of skew between signal lines has hitherto prevented wide interfaces from operating at high frequency, hence creating a fundamental limit to the bandwidth than an interface can carry.
In another example, that of Automatic Test Equipment (ATE), a substantial complexity of deskew circuitry has been required to test high speed devices. Moreover, as soon as the device is under test, the heat generated by the environment of the drivers, the drivers themselves and other factors has caused the skew to alter during the test.
Known is the use of analogue increments to automatically self-calibrate a pulse generator described in U.S. Pat. No. 5,430,660. During the calibration, the output of the oscillator is used to produce output pulses whose edge locations are then adjusted by small digital increments or “slivers” and very small analogue increments or “verniers”. The RAM contents are converted to a serial bit stream that controls the coarse pulse width and period as an integral number of top octave periods, or quanta. However, this method of skew control is not automatic and requires an operator to disconnect the generator from the working circuit and connect an output of the generator to a calibration input in order to accomplish the calibration.
It has been a growing tendency in high speed communications, in particular, digital systems of data transmission, to increase data transmission rates and timing accuracy. However, as frequency grows, a problem arises of accurate and reliable reading of previous and subsequent symbols by various devices for receiving and transmitting data.
For digital circuit devices such as flip-flops, latches and other storage circuits, accurate reading of signals is possible only provided strict requirements to set-up and hold times are observed, where “set-up time” is the time before the clock edge during which data are required to be present and stable, and “hold time” is the time after the clock edge during which data are required to be present and stable. These requirements result in that the maximum clock frequency is limited by the sum of hold and set-up times; therefore, it is desirable that set-up and hold time be as short as possible.
Different attempts have been made to improve setup and hold time characteristics, however, a thorough analysis of component elements of setup/hold times is absent in the available art, therefore, it would be helpful to gain a better understanding of phenomena taking place at that.
In
FIG. 7
a
, a block scheme of a real flip-flop is presented, which consists of an ideal flip-flop FF which is noiseless, hysteresis-free and has zero setup and hold times. A real flip-flop additionally comprises delays Td and Tc in data and clock paths, respectively. Also, there is a source N of phase noise in clock path and a source of hysteresis H.
The delays Td and Tc depend on such parameters as temperature, supply voltage, direction of transition (rising or falling edge), frequency of signal and others. The combination of Td and Tc gives a value of setup/hold time which provides stable data transmission. For example, assuming Td varies from 0 to 1 ns, Tc varies from 0 to 1 ns, each independently, it would be impossible to read data earlier than 1 ns after the change occurs, with respect to clock, or less than 1 ns before the change that gives the values of setup time=1 ns, hold time=1 ns. Furthermore, phase noise extends setup and hold times for the value of phase noise.
Flip-flops are often used to synchronize signals operating at different frequencies to a local clock. However, since the signals are asynchronous to the local clock, the setup and hold time specifications associated with the flip-flop are sure to be violated. When the setup and hold time is violated, the output response of the flip-flop is uncertain. The output may assume a “metastable” state, defined as the time period during which the output of a digital logic device is not at logic level 1 or logic level 0, but instead resides at an output level between logic level 0 and logic level 1. The voltage ranges corresponding to different logic levels are specified by the manufacturer of the device. For bipolar TTL technology, for example, the metastable region might lie between 0.8 volts and 2.0 volts.
The metastable problem occurs when the signal being input to the flip-flop is undergoing a transition from one logic level to the other simultaneously with the active edge of the local clock pulse, causing the latch section of the flip-flop to latch at the intermediate voltage level. Since the input data is changing while it is being clocked, the system designer does not care if the flip-flop goes to either a high or low logic level in this instance, just so long as the output does not “hang-up” in the metastable region. Eventually, the output of the flip-flop will stabilize at a valid logic level; however, logic circuitry following the flip-flop depends upon the delay specification (stated time period from the clock pulse to a valid output) being met. A metastable output may cause this logic circuitry to fail. Thus, the metastable characteristics of the flip-flop used to synchronize an asynchronous data stream can influence overall system reliability.
One approach to mitigate the problem of metastable outputs is to provide a second flip-flop in series with the first flip-flop, or more flip-flops cascaded as proposed in U.S. Pat. No. 4,929,850. The clock to the second flip-flop is delayed relative to clock to the first flip-flop, thus allowing time for the output signal of the first flip-flop to stabilize at a valid logic level before clocking the data into the second flip-flop. In many applications, this delay is excessive. Furthermore, the logic may still fail if the output of the first flip-flop remains in the metastable region for a period greater than the delay between the clocks.
Thus, the traditional solution of employing two serially connected flip flops is not desirable in applications where an output is needed rapidly. The use of the second flip flop delays the resulting output by an entire clock period. In order to rapidly provide this output, it has also been proposed to rapidly resolve internal logic signals through the use of the deselect synchronizer, instead of two flip flops.
Another approach is described in U.S. Pat. No. 6,002,282 according to which a closed-loop clock delay adjustment system compensates the difference between the delay introdu

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