Timing control in data receivers and transmitters

Details Timing control in data receivers and transmitters Timing control in data receivers and transmitters

2007-01-02

2007-01-02

Kumar, Pankaj (Department: 2611)

Pulse or digital communications

Transceivers

C375S222000, C375S295000, C375S316000

Reexamination Certificate

active

10335909

ABSTRACT:
A Gigabit transceiver (1) has a receiver (2) and a transmitter (3). There is an ADC (5) in the receiver (2) for each channel (A, B, C, D). The ADCs (5) oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs (2) operate off half of the oversampling rate. In the receiver (2) fractionally spaced equalisers (FSES,6) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.

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