Timing control for precharged circuit

Details Timing control for precharged circuit Timing control for precharged circuit

1991-11-29

1993-06-29

Hoff, Marc

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

341155, 307448, H03M 112

Patent

active

052238342

ABSTRACT:
A timing control for precharged digital circuits to avoid spurious error appearing at the output due to the slow pull-down of the precharged node after precharging. A NAND gate is used to delay the precharged node siganl transmitting to the output stage until the precharged node is fully discharged. This timing control circuit is used to prevent any spurious peaking of the output of an analog-to-digital converter using precharged bit lines.

REFERENCES:
patent: 4250494 (1981-02-01), Butler et al.
patent: 4633107 (1986-12-01), Norsworthy
patent: 4857764 (1989-08-01), Young
patent: 4883989 (1989-11-01), Mizukami

Affiliated with

Also associated with

Rating

Timing control for precharged circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing control for precharged circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing control for precharged circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1758706