Timing control circuit for synchronous static random access memo

Details Timing control circuit for synchronous static random access memo Timing control circuit for synchronous static random access memo

1995-08-14

1996-09-24

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365191, 365194, G11C 800

Patent

active

055597521

ABSTRACT:
A timing control circuit (10) is disclosed that provides a timing circuit (12) for controlling the operation of an I/O path circuit (14) in a synchronous static random access memory (SRAM). In a read or write operation, the timing circuit (12) sequentially disables bit line equalization circuits (34), enables sense amplifiers (38), disables I/O line equalization circuits (42), and enables secondary sense amplifiers (44). Further, the timing control (12) initiates a reset operation prior to the completion of the read or write operation. The reset operation includes sequentially enabling the bit line equalization circuits (34), disabling the sense amplifiers (38), enabling the I/O line equalization circuits (42), and disabling the secondary sense amplifiers (44). The timing circuit (12) includes first, second and third delay circuits (20, 22, and 24) to allow for minimum split times for bit line pairs (32) and I/O line pairs (40), and minimum secondary sense amplifier (44) sensing times.

REFERENCES:
patent: 5091889 (1992-02-01), Hamano
patent: 5291447 (1994-03-01), Kodama
patent: 5473565 (1995-12-01), Kusakari
patent: 5479374 (1995-12-01), Kobayashi

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