Timing circuit means

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

328131, 361197, H03K 513, G01R 2902, H01H 4732

Patent

active

040177467

ABSTRACT:
A timing circuit is shown as employing a flip-flop for driving an output circuit portion as to have such output circuit portion in effect provide either a low or no output or a high output with such in turn being employed for turning on or turning off a related power circuit; a first high gain amplifier is employed as a means for placing the flip-flop into one of its states whenever an appropriate trigger signal is momentarily applied thereto, while a second high gain comparator amplifier is effective to provide a reset signal to the flip-flop whenever a particular span of time has elapsed from the application of the trigger signal; the timing for creating the reset signal is achieved as through an R-C network which provides, in effect, a threshold signal to the second amplifier upon the application of which the second amplifier produces the reset signal and applies it to the flip-flop thereby placing the output circuit portion in a condition wherein it has either a low or no output. Additional defeat or inhibiting means are provided to cause the output circuit portion to be placed in such a condition of either low or no output even if the timing phase of the overall cycle has not been completed.

REFERENCES:
patent: 3165644 (1965-01-01), Clapper
patent: 3388346 (1968-06-01), Roof et al.
patent: 3660692 (1972-05-01), Bartlett
patent: 3735154 (1973-05-01), Meeker et al.
patent: 3909635 (1975-09-01), Maida

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