Timing circuit including jitter compensation

Details Timing circuit including jitter compensation Timing circuit including jitter compensation

1987-02-26

1989-07-11

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

375120, 370102, H04L 708

Patent

active

048478750

ABSTRACT:
An output timing signal is generated by a phase locked loop. The loop includes a phase detector, a low-pass filter and a voltage controlled oscillator. A reference signal that is in synchronism with an incoming digital signal is divided by a first divisor to generate a reference clock signal. The reference clock signal is supplied as a first input to the phase detector. A phase clock signal is generated in the loop by dividing the output timing signal by a second predetermined divisor. The phase clock signal is supplied as a second input to the phase detector to generate an error signal for controlling the oscillator. The first and second divisors are selected to eliminate jitter caused by large gaps in the incoming digital signal resulting from overhead bit removal. Additionally, the phase clock signal is controllably compensated to cause variations in the bit rate of the output timing signal which correspond to variations in the actual data rate of the incoming digital signal because of stuffing bits. The compensation of the phase clock signal is dependent on the number of data bits and the number of non-data bits in the stuffing bit positions.

REFERENCES:
patent: 4061973 (1977-12-01), Reimers et al.
patent: 4166979 (1979-09-01), Waggener
patent: 4651026 (1987-03-01), Serfaty et al.
patent: 4654859 (1987-03-01), Kung et al.
patent: 4759041 (1988-07-01), Anderson et al.
patent: 4771426 (1988-09-01), Rattlingourd et al.
"Phase-Locked Loop", Transmission Systems for Communications, Fifth Edition, Bell Telephone Laboratories, Incorporated, 1982, pp. 688-692.

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