Timing circuit for single line serial data

Details Timing circuit for single line serial data Timing circuit for single line serial data

1991-02-12

1992-02-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307571, 307262, 328 63, 328 72, H03K 1992, H03K 1716

Patent

active

050878280

ABSTRACT:
A timing adjusting circuit for single line serial data includes a synchronous data sampling circuit for sampling data input from the exterior synchronously with a reference clock pulse, a data edge detection circuit for outputting data edge detection signals, and a synchronous pulse generation circuit for generating repetitive pulses synchronized with output from the data edge detection circuit. The timing circuit further includes an inversion circuit for inverting branched part of the reference clock pulse, a sub-data sampling circuit for sampling the branched data at the inverted reference clock pulse, a sub-data edge detection circuit for outputting edge detection signals synchronized with the inverted reference clock pulse, a sub-synchronous pulse generation circuit for generating repetitive pulses synchronized with output from the data edge detection circuit, an adder for performing logical addition of output of the synchronous and sub-synchronous pulse generation circuits, an adder for performing logical OR of output of the data sampling and edge detection circuits, a waveform shaping circuit for eliminating extraneous signals, and an output timing circuit for adjusting timing of output data and synchronous clock pulse output from the waveform shaping circuit.

REFERENCES:
patent: 4737722 (1988-04-01), Ramesh et al.
patent: 4989223 (1991-01-01), Katayose et al.

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