Timing circuit for memory employing reset function

Details Timing circuit for memory employing reset function Timing circuit for memory employing reset function

1988-12-27

1991-05-21

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

365210, G11C 800, G11C 702

Patent

active

050181114

ABSTRACT:
A timing circuit is described for a single phase clocked memory. The output of a flip-flop is used to initiate the generation of a plurality of control signals through models of circuit elements of the memory such as the word line, bit line, etc. The output of these models are used to generate control signals both when the flip-flop is set and reset. The flip-flop is reset by a signal from one of the models.

REFERENCES:
patent: 3778784 (1973-12-01), Karp et al.
patent: 3959781 (1976-05-01), Mebta et al.
patent: 4087704 (1978-05-01), Mebta et al.
patent: 4496861 (1985-01-01), Bazes
patent: 4558435 (1985-12-01), Hsieh
patent: 4644501 (1987-02-01), Nagasawa
patent: 4689772 (1987-08-01), Jordy et al.

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