Timing circuit for high voltage testing

Details Timing circuit for high voltage testing Timing circuit for high voltage testing

1999-09-20

2001-03-13

Phan, Trong (Department: 2818)

Static information storage and retrieval

Powering

C365S194000, C365S191000

Reexamination Certificate

active

06201752

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an integrated circuit and more particularly to an integrated circuit with a timing circuit for high voltage testing.
BACKGROUND OF THE INVENTION
Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology require ever increasing clock rates and memory bus widths to achieve high data rates. These high data rates, however, are subject to practical limitations. An optimal memory circuit designed for a normal range of supply voltage and temperature may fail to operate correctly under high voltage and high temperature conditions required by a burn in test. A memory circuit functioning at a normal high voltage and high temperature limit of 3.6 V and 90° C., for example, may fail to operate at a burn in condition of 6.5 V and 125° C.
A particular failure mode occurs when a word line is activated and initial data from a memory cell is applied to complementary bit lines. A column decode circuit prematurely couples a selected column to a data lead before a sense amplifier amplifies the data. This premature coupling is due to the increased operating speed at the 6.5 V supply voltage. Moreover, a second data amplifier is also activated prematurely due to increased operating speed and incorrectly reads the data on the data lead. Thus, an optimal design for normal operating conditions may fail a burn in test. A reduction in burn in conditions would result in an inordinate increase in burn in test time. Alternatively, a relaxation in circuit timing would greatly compromise circuit performance under normal operating conditions.
SUMMARY OF THE INVENTION
These problems are resolved by a circuit with a detector circuit coupled between a supply voltage terminal and a reference voltage terminal. The detector circuit produces a first control signal in response to a detected mode and a second control signal in response to another mode. A first circuit including a delay circuit receives the first control signal and a third control signal. The first circuit produces a fourth control signal at an output terminal in response to the first and third control signals. A second circuit receives the second control signal and the third control signal. The second circuit produces the fourth control signal to the output terminal in response to the second and third control signals.
The present invention provides a normal and a delayed control signal for activating a data path. The delayed control signal compensates for circuit operation at high voltage.


REFERENCES:
patent: 5996096 (1999-11-01), Dell et al.
patent: 6115319 (2000-09-01), Kimoshita et al.

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