Timing circuit

Details Timing circuit Timing circuit

1995-08-25

1997-02-25

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Including memory

377 77, G06M 300

Patent

active

056065841

ABSTRACT:
The current invention provides a timer circuit for timing a plurality of time periods. The timer circuit has a timing pulse input for receiving timing pulses; a set of state outputs being at a set of logic states, each logic state taking one of two logic values, the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs, each providing a signal at the expiry of a predetermined time period; and a resetting signal for resetting the timing circuit and for defining an initial set of logic states. The set of logic states follows a first sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within each set are at a first logic value (1) except at least one logic state, which is at a second logic value (0), different state outputs carrying the excepted state(s) in each of the sets of logic values within the first sequence of sets of logic values.
A first timing signal generator generates a first timing signal to indicate the expiry of a first time period by detecting the first occurrence of the second logic value (0), in a subset of the set of logic states at the set of state outputs. A second timing signal generator generates a second timing signal to indicate the expiry of a second time period by detecting a predetermined combination of logic values at the set of state outputs.

REFERENCES:
patent: 3896388 (1975-07-01), Hatsukano et al.
patent: 5073909 (1991-12-01), Kotzin et al.
patent: 5090035 (1992-02-01), Murase
Hack, G. E., "Universal Counter Function Utilizing A Shift Register Latch String," IBM Technical Disclosure Bulletin, 27:1A, Jun., 1984, pp. 181-182.
Holdsworth, B. et al., "More shift registers--ring counters and maximum-length sequence generators," Wireless World 83:1053, Nov., 1977, pp. 72-76.
Argytoudis, P. et al., "Shift-register applications reach gigahertz range," EDN Electrical Design News 32:11, May 28, 1987, pp. 195-200.
Tokarnia, A., "Minimal Shift Counters and Frequency Division," 30th ACM/IEEE Design Automation Conference, Jun. 1993, Dallas, Texas, pp. 19-24.
Clark, D. W. et al., "Maximal and Near-Maximal Shift Register Sequences: Efficient Event Counters and Easy Discrete Logarithms," IEEE Transactions On Computers, 43:5, May, 1994, pp. 560-567.

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