Timing calibration and timing calibration verification of...

Details Timing calibration and timing calibration verification of... Timing calibration and timing calibration verification of...

2001-08-07

2003-05-27

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06570397

ABSTRACT:

TECHNICAL FIELD
This invention relates to systems and methods for timing calibration and timing calibration verification of electronic circuit testers.
BACKGROUND
Electronic circuit testers are designed to test the performance of a device or an integrated circuit. An electronic circuit tester may be used to test finished packaged devices and integrated circuits at various stages of manufacture of the device or an integrated circuit from the initial wafer processing stage to the final packaging stage.
A conventional programmable electronic circuit tester typically includes a test head that is electrically connected to one or more racks of electronic test and measurement instruments (e.g., ac and dc electrical signal generators, and signal analyzers, such as an oscilloscope and a network analyzer). The test head typically interfaces to a device or an integrated circuit through a load board that, in turn, is connected to a probe card (or fixture board). An electronic circuit tester typically includes a separate test channel for each terminal of a device to be tested. Each test channel may transmit a test signal to a device terminal or may receive and process a device output signal appearing at the device terminal. The load board and probe card assemblies provide signal paths between the circuit boards that are mounted in the test head and the terminals of a device to be tested. In general, the configuration of the load board depends on the category (e.g., analog or digital) of device or integrated circuit being tested. The configuration of the probe card, on the other hand, typically is specific to the family of device or integrated circuit being tested. The test head may be mounted pivotally on a dolly or other adjustable support mechanism so that the electronic circuit tester may be used to test both packaged devices and integrated circuits.
A typical electronic circuit tester tests a device under test (DUT) by applying test signals of various logic states to DUT input terminals. The states of the signals that are produced at DUT output terminals in response to the applied test signals are monitored to determine whether the DUT is behaving as expected. Each test channel includes a tristate driver for supplying a test signal to a DUT input terminal and a comparator for producing output data corresponding to the state of the DUT output signal produced at the DUT output terminal. A test typically is organized into a succession of test cycles. A channel may carry out one or more actions during a test cycle, including driving a test signal, tristating a test signal, and sampling a DUT output signal and comparing the sampled signal to expected states of the DUT terminal. Each test channel receives ACTION and TIMING data for each test cycle. A formatting and timing circuit within each test channel responds to the ACTION and TIMING data by producing three control signals: “TRISTATE,” “DRIVE” and “COMPARE.” The TRISTATE signal tristates the channel's driver and the DRIVE signal indicates whether the driver's output test signal is to be of a high or low logic level. The COMPARE signal controls when the comparator samples the state of the DUT output signal. The ACTION data input to the formatting and timing circuit indicates which of the DRIVE, TRISTATE, and COMPARE signals are to change state during a next test cycle, whereas the TIMING data indicates the times during the test cycle at which those state changes are to occur.
An electronic circuit tester must maintain extremely accurate tolerances so that the performance of a DUT may be characterized accurately. To this end, the timing and formatting circuit within each test channel must advance state changes in their DRIVE and TRISTATE output signals and delay state changes in their COMPARE output signals from the times indicated by their input TIMING data to account for signal path delays that are inherent in each test channel. Since the drive and compare signal path delays may vary from channel-to-channel, it is necessary to separately measure signal path delays for each channel during calibration.
The timing calibration of an electronic circuit tester may be performed manually with external measurement instruments. For example, voltmeters may be used to test voltage levels and oscilloscopes may be used to evaluate timing characteristics of each test channel of an electronic circuit tester. However, external testing of an electronic circuit tester is extremely time consuming, especially for high pin count electronic circuit testers. In an alternative approach, a calibration board may be connected to a test head to calibrate an electronic circuit tester (see, e.g., U.S. Pat. No. 5,539,305). Typically, an electronic circuit tester is calibrated based upon calibration standards, such as opens and shorts, that are connected serially to the test connectors of the test head. One conventional calibration method involves serially calibrating the timing of each test head pin with respect to a reference signal. The results of each measurement are stored in a storage device, such as a capture memory. After all the of the test head pins have been measured, a processor within the electronic circuit tester calibrates each test channel based upon the data stored in the capture memory.
In addition to the various timing calibration methods that have been proposed, techniques for verifying the timing calibration of electronic circuit testers have been developed. For example, manufacturers of electronic circuit testers typically provide a set of built-in-test (BIT) routines in which the drivers and receivers of a single selected pin are calibrated with respect to all of the other pins in the system. In accordance with this approach, the selected pin is connected to each of the other pins by cables and relays, one at a time. U.S. Pat. No. 6,192,496 describes another timing calibration verification approach in which a specially configured DUT board selectively shorts adjacent test channel lines together. In this way, each test channel may act as a sender and a receiver for a corresponding test channel so that the propagation delay of each test channel may be tested against the propagation delay of another test channel. In another timing calibration verification method, the specialized DUT board may be removed from the test head, so that each connector pin is disposed as an open circuit. This no-load condition results in maximum impedance mismatch within the line, and therefore maximizes the signal reflection back toward the driver. The receiver (companion receiver to the driver) may be configured to sense this reflection and, thereby, determine the timing of the signal (and therefore the cable length) between the driver and the connector pins in a time domain reflectometer measurement (TDR) test.
SUMMARY
The invention features novel systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers.
In one aspect, the invention features a system for calibrating an electronic circuit tester that includes a substrate, a connector interface, and a calibration circuit. The substrate is mountable on a test head of an electronic circuit tester, the test head having a plurality of test connectors terminating substantially in a plane. The connector interface is disposed on the substrate and comprises a plurality of test connector contact pads that are exposed for electrical contact with the test connectors. The calibration circuit is supported by the substrate and is electrically connected to the connector interface. The calibration circuit also is operable to connect test connectors to a source of a calibration reference signal and to one or more selected test connectors in accordance with protocols for calibrating the electronic circuit tester to the plane of the test connectors and verifying calibration of the electronic circuit tester.
Embodiments in accordance with this aspect of the invention may include one or more of the following features.
The connector interface prefe

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