Timing and control circuit for a static RAM responsive to an add

Details Timing and control circuit for a static RAM responsive to an add Timing and control circuit for a static RAM responsive to an add

1992-02-04

1994-07-05

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36518908, 36523001, 365233, 307480, G11C 702

Patent

active

053273940

ABSTRACT:
An SRAM having an input address bus, a memory array and coupled sense amplifiers, internal sense amp enable and output data bus enable nodes further includes a circuit for generating an asynchronous address transition signal from a series of address signals received on the input address bus, and a timing and control circuit. The timing and control circuit selects a single address signal and suppresses the other address signals within a predetermined period of time such as the normal cycle time of the SRAM. If the address transition signal includes a pulse train of two or more pulses spaced apart by less than the predetermined time interval, the timing and control circuit generates fixed pulse width sense amp enable and output data bus enable signals corresponding to the last pulse in the pulse train. If the pulses are spaced apart by more than the predetermined time interval, the timing and control circuit generates fixed pulse width sense amp enable and output data bus enable signals corresponding to each pulse in the pulse train of the address transition signal. If the address transition signal is a single pulse having a variable pulse width related to the number of different address signals received on the address bus, the timing and control circuit generates fixed pulse width sense amp enable and output data bus enable signals corresponding to the single pulse of the address transition signal.

REFERENCES:
patent: 4636991 (1987-01-01), Flannagan et al.
patent: 4661931 (1987-04-01), Flannagan et al.
patent: 4744063 (1988-05-01), Ohtani et al.
patent: 4827454 (1989-05-01), Okazaki
patent: 4947379 (1990-08-01), Okuyama
patent: 5025422 (1991-06-01), Moriwaki et al.
patent: 5159574 (1992-10-01), Kim et al.
patent: 5198708 (1993-03-01), Gillingham
patent: 5198709 (1993-03-01), O'Connell
patent: 5268873 (1993-12-01), Suzuki
patent: 5268874 (1993-12-01), Yamauchi
patent: 5295117 (1994-03-01), Okada
Micron Technology, Inc., "MOS Data Book", Jan. 1991, pp. 4-151 to 4-164.

Affiliated with

Also associated with

Rating

Timing and control circuit for a static RAM responsive to an add does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing and control circuit for a static RAM responsive to an add, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing and control circuit for a static RAM responsive to an add will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-801637