Timing analysis when integrating multiple circuit blocks...

Details Timing analysis when integrating multiple circuit blocks... Timing analysis when integrating multiple circuit blocks...

2011-06-14

2011-06-14

Doan, Nghia M (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S100000, C716S101000, C716S102000, C716S103000, C716S106000, C716S113000, C716S126000, C716S129000, C716S131000, C716S134000

Reexamination Certificate

active

07962872

ABSTRACT:
An aspect of the present invention provides for timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy. In an embodiment, an optimized model for a circuit block is created by combining information provided by two different models of the same circuit block and performing timing analysis based on the optimized model. In an embodiment, the two models correspond to black box and interface timing models. In the optimized model, ports for which only timing arc information is deemed necessary are modeled using corresponding information from the black box model, while ports for which more accurate or detailed information is deemed necessary are modeled using corresponding information from the interface timing model. The optimized model enables the integration to be performed with a balance of resource requirements and accuracy.

REFERENCES:
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patent: 6952816 (2005-10-01), Gupta et al.
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patent: 7328415 (2008-02-01), Bou-Ghazale et al.
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patent: 7356451 (2008-04-01), Moon et al.

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