Timing analysis method and apparatus for enhancing accuracy...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing

Reexamination Certificate

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C716S108000, C716S113000

Reexamination Certificate

active

08000951

ABSTRACT:
A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when performing circuit analysis by partitioning a circuit into blocks, the SPICE deck generating section generates a SPICE deck by interconnecting the blocks, for a path that needs analysis, by using a result of static timing analysis and using simulation conditions for the each block. The feedback-based static timing analyzing section causes a result of the simulation performed using the generated SPICE deck to be reflected in the static timing analysis.

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Marco Delaurenti, Design and Optimization Techniques of High-Speed VLSI Circuits, PhD Dissertation, Dec. 1999, p. 83.

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