Timing analysis for logic optimization using target library dela

Details Timing analysis for logic optimization using target library dela Timing analysis for logic optimization using target library dela

1994-05-26

1995-12-12

Teska, Kevin J.

Boots, shoes, and leggings

364489, 395550, G06F 1125

Patent

active

054756057

ABSTRACT:
A computer automated logic synthesis tool performs a timing analysis during the optimization of a hardware description file including general logic expressions of a prototype circuit by minimizing a delay value for a gate network comprised of logic cells provided in a target library. Minimization occurs by modeling a gate network for a logic expression that orders the input signals into the gate network according to their input delays, and the output delays from assigned logic cells. The output delay for the assigned logic cell is based on intrinsic delays of boolean nodes in the logic cells. The delay for the gate network includes an R-C delay value for gate fan-out, based on the average R-C delay values in the target library. The logic synthesis tool is able to select from among various alternate logically equivalent gate networks, the gate network that provides the minimized timing delay.

REFERENCES:
patent: 5168455 (1992-12-01), Hooper
patent: 5210700 (1993-05-01), Tom
patent: 5287289 (1994-02-01), Kageyama et al.
patent: 5293327 (1994-03-01), Ikeda et al.
patent: 5305229 (1994-04-01), Dhar
patent: 5333032 (1994-07-01), Matsumoto et al.
patent: 5353433 (1994-10-01), Sherman
patent: 5359535 (1994-10-01), Djaja et al.
patent: 5365463 (1994-11-01), Donath et al.
patent: 5381345 (1995-01-01), Takegami et al.
patent: 5384720 (1995-01-01), Ku et al.
Burnstein, M. and Youssef, M., "Timing Influenced Layout Design" IEEE, 22nd Design Automation Conference; Paper 9.2, 124-130, 1985.
Berman, C. L. et al., "Efficient Techniques for Timing Correction" IEEE, 415-419, 1990.
Singh, K. J. et al., "Timing Optimization of Combinational Logic" IEEE, 282-285, 1988.
Chen, K. C. and Muroga, Saburo, "Timing Optimization for Multi-Level Combinational Networks" IEEE, 27th ACM/IEEE Design Automation Conference, Paper 21.1, 339-344, 1990.
Teig, S. et al., "Timing-Driven Layout of Cell-Based ICs" VLSI Systems Design, 63-73, May 1986.
Dunlop, A. E et al., "Chip Layout Optimization Using Critical Path Weighting" IEEE, 21st Design Automation Conference, Paper 9.2 133-136, 1984.

Affiliated with

Also associated with

Rating

Timing analysis for logic optimization using target library dela does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing analysis for logic optimization using target library dela, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing analysis for logic optimization using target library dela will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1365319