Timing adjustment circuit for digital switching

Details Timing adjustment circuit for digital switching Timing adjustment circuit for digital switching

1978-11-13

1981-05-26

Stewart, David L.

Multiplex communications

Wide area network

Packet switching

H04J 307

Patent

active

042702038

ABSTRACT:
A slip-free timing adjustment system adjusts channel timing for a multiplexed digital data stream. The data stream in each of c time division channels (10, 11) is modified preparatory to switching in a digital time-division circuit switch (14). The multiplexed digital data stream may arrive at the switch at a rate R0. The switch clock rate may be at a rate R1. Rates R0 and R1 are potentially different.
Signal means (12, 13) provide for inserting a variable length timing code, one bit at a time, in each of the c channels in each multiplexed digital data stream. The multibit timing code is composed of successive variable length code words of length L and L+1 bits.
Adjustment means (18, 42) receives the multiplexed data stream and adjusts individual channel rates in each of the c channels. This includes means for altering the length of the variable length code words by adjusting code words of length L to code words of length L+1 when the input clock is slower than the switch clock and for adjusting code words of length L+1 equal to code words of length L when the input clock is faster than the switch clock. By this means, the respective clock rates are equalized by the adjustment of just a sufficient set of code words in each of said channels to result in equal rates.
Means (24, 28, 25, 29, 43, 44, 45) provide for transmitting the adjusted time-division multiplexed channels to a digital-time-division switch (14) for channel switching under control of the switch clock (21).

REFERENCES:
patent: 3646271 (1972-02-01), Shigaki
patent: 3970796 (1976-07-01), Gyurki
patent: 4053715 (1977-10-01), Drapkin
patent: 4156111 (1979-05-01), Downey
IEEE Transactions on Communication Technology; vol. COM-16, No. 2; Apr. 1968; "Synchronization of PCM Channels by . . . Word Stuffing," by Butman.
Witt, F. J., "An Experimental 224 Mb/S Digital Multiplexer-Demultiplexer Using Pulse Stuffing Synchronization," Bell Systems Technical Journal, Nov. 1965, pp. 1843-1885.
Abate, J. E., Brandenburg, L. H., Lawson, J. C., and Ross, W. L., "The Switched Digital Network Plan," Bell System Technical Journal, Sep. 1977, pp. 1297-1320.
Gersho, A., and Karafin, B. J., "Mutual Synchronization of Geographically Separated Oscillators," Bell Systems Technical Journal, Dec. 1966, pp. 1689-1704.
Brilliant, M. B., "The Determination of Frequency in Synchronized Oscillators," Bell Systems Technical Journal, Dec. 1966, pp. 1737-1748.

Affiliated with

Also associated with

Rating

Timing adjustment circuit for digital switching does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing adjustment circuit for digital switching, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing adjustment circuit for digital switching will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-456576