Timing adjustment circuit and method thereof

Details Timing adjustment circuit and method thereof Timing adjustment circuit and method thereof

2008-05-20

2008-05-20

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

11515850

ABSTRACT:
A timing adjustment circuit and method thereof are disclosed. The timing adjustment circuit at least consists of a second timing adjustment unit, a multistage sample circuit, and a decision circuit for adjusting received timing of an output signal transmitted by a first chip and received by a second chip. The method takes advantage of the multistage sample circuit to receive a clock signal of receiving end so as to generate a plurality of sample clock signal. Later, according to the sample clock signals, sample output signals to generate a plurality of sampled signal. At last, make comparison of the sampled signals by the decision circuit in accordance with the output signals to generate a second adjustment signal being transmitted to the second timing adjustment unit for adjusting phase of a base clock to generate an adjusted receiving-end clock signal. Thus the receiving timing of the second chip to receive the output signal is adjusted. Moreover, the decision circuit sends a first adjustment signal to a first timing adjustment unit of the timing adjustment circuit for generating an adjusted output-end clock signal. Thus the output timing that the first chip transmits the output signal to the second chip is adjusted.

REFERENCES:
patent: 5278873 (1994-01-01), Lowrey et al.
patent: 6870415 (2005-03-01), Zhang et al.

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