Timer lockout circuit for synchronous applications

Details Timer lockout circuit for synchronous applications Timer lockout circuit for synchronous applications

2006-06-27

2006-06-27

Mai, Son (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S203000

Reexamination Certificate

active

07068564

ABSTRACT:
A SDRAM mid a tinier lockout circuit. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and a circuit for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.

REFERENCES:
patent: 6353573 (2002-03-01), Koshikawa
patent: 6434082 (2002-08-01), Hovis et al.
patent: 6507526 (2003-01-01), Ohtake
patent: 2003/0185075 (2003-10-01), Park et al.

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