Timer circuit including an analog ramp generator and a CMOS coun

Details Timer circuit including an analog ramp generator and a CMOS coun Timer circuit including an analog ramp generator and a CMOS coun

1991-04-01

1992-06-23

Callahan, Timothy P.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307273, 307603, 307608, 328 55, 377110, H03K 513, H03K 3284

Patent

active

051245973

ABSTRACT:
A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing conrol signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.

REFERENCES:
patent: 3576496 (1971-04-01), Garagnon
patent: 4604536 (1986-08-01), Clutterbuck et al.
patent: 4611136 (1986-09-01), Fujie
patent: 4843255 (1989-06-01), Steubing
patent: 4857760 (1989-08-01), Steubing
patent: 4954784 (1990-09-01), Kitamura
Motorola Product Preview, Synchronous Presettable Binary Counter, Chapter 5, pp. 88-96.
National Semiconductor product catalog, Synchronous Presettable Binary Counter, Chapter 4, pp. 83-89.
Texas Instruments product catalog, Synchronous 4-Bit Decade and Binary Counters, chapter 2, pp. 217-230.
Signetics product catalog, Presettable Synchronous 4-Bit Binary Counter; Asynchronous Reset, chapter 7, pp. 212-218.
Linsay Kleeman and Antonio Cantoni, Metastable Behavior in Digital Systems, IEEE Design & Test of Computers, Dec. 1987, pp. 1-19.

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