Timer bus structure for an integrated circuit

Details Timer bus structure for an integrated circuit Timer bus structure for an integrated circuit

1995-11-13

1998-09-22

Butler, Dennis M.

395306, 395559, G06F 1340, G06F 104

Patent

active

058128336

ABSTRACT:
I/O control modules (25-29) include a timer bus (71, 72) which may be segmented anywhere along its length. As a result, the channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebases by their respective timer bus (71, 72). The channels within one timer bus block (e.g. 86) can be used to perform different function(s) with the potential for no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). In one embodiment, one end of each timer bus (71, 72) is delineated by a master timer bus control channel (61, 63), and the other end of the timer bus is delineated by a slave timer bus control channel (62, 64).

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