Timer architecture for multi-task computers and for serial data

Details Timer architecture for multi-task computers and for serial data Timer architecture for multi-task computers and for serial data

1988-01-28

1989-11-07

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Counter controlled counter

377 52, 377 56, 377110, 377 20, 368156, 3281301, H03K 2138, H03K 2110

Patent

active

048797332

ABSTRACT:
A timer which can be used to provide interrupt signals at predetermined but variable periods for multi-tasking microcomputers or serial data acquisition in pagers comprises a plurality of modulo counters. Each modulo counter has selectable clock inputs and has an output coupled via switches to a NOR gate and to the other modulo counters. Programmable configuring means control the switching means to configure the counters so as to produce desired outputs at the logic gate. The configuring means can also reset the modulus of the modulo counters to any desired value. Thus, the timer produces variable interrupt signals with little or no overhead processor time.

REFERENCES:
patent: 3639844 (1972-02-01), Karklys
patent: 4035661 (1977-07-01), Carlson
patent: 4131855 (1978-12-01), Hamagawa
patent: 4184320 (1980-01-01), Kashio
patent: 4185283 (1980-01-01), Clark
patent: 4376995 (1983-03-01), Shimizu
patent: 4489422 (1984-12-01), Paradise et al.
Mitsubishi Microcontrollers, M50930-XXXFP, 8 Bit Single-Chip CMOS Microcontrollers, Feb., 1987, pp. 8-11, Publication #MDS-740-03-0287-5K.

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