Timeout process circuit and receiver including this timout proce

Details Timeout process circuit and receiver including this timout proce Timeout process circuit and receiver including this timout proce

1995-01-26

1998-01-06

Teska, Kevin J.

Boots, shoes, and leggings

395550, 3642678, 3642719, G06F 1300

Patent

active

057064253

ABSTRACT:
A timeout process circuit for performing a timeout detection process incorporated in a receiver, having a timer for incrementing time data indicating a current time, a memory including data table to store a reception time of the cell most recently received by the receiver, a register for storing a timeout value indicating a maximum permitted time interval of cell reception, a controller for reading out the reception time stored in the data table the controller receiving the timeout detection start signal from the timer, an adder for adding the reception time from the data table and the timeout value stored in the first register means, a comparator for comparing the result of the addition by the adder with the time data from the timer, and a decision circuit for receiving the comparison result from the comparator and deciding whether or not the cell of the frame in the reassembly is a timeout based on the comparison result. In the timeout process circuit, the reception time of the cell is stored in the data table when the cell is received by the receiver.

REFERENCES:
patent: 3623019 (1971-11-01), Groth
patent: 5012435 (1991-04-01), Bailey et al.
patent: 5471564 (1995-11-01), Dennis et al.
patent: 5490153 (1996-02-01), Gregg et al.
patent: 5515385 (1996-05-01), Fulling et al.
Kurano et al., "Gig-A-Bit ATM Cross-Connect System With STM-ATM Conversion Function", IEEE Communications Society, pp. 1461-1467, (1993).
Guillemin et al., "The Spacer-Controller: Architecture and First Assessments" Broadband Communications, Proc. IFIT TC6 Workshop on Broadband Communications, pp. 313-323, (1992).

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