Timed circuit simulation in hardware using FPGAs

Details Timed circuit simulation in hardware using FPGAs Timed circuit simulation in hardware using FPGAs

1997-01-10

2000-02-22

Teska, Kevin J.

39550034, 39550036, 39550037, 39550038, G06F 1750

Patent

active

060289937

ABSTRACT:
A logic circuit is simulated for mapping and emulation on a field programmable gate array-based platform by mapping one or more of the circuit delays onto delay elements in the FPGA-based platform. The operations of the delay elements are controlled by one or more simulations clocks that are different from any user-specified clocks.

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