Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1998-09-02
2001-04-03
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S208000, C327S210000, C327S211000
Reexamination Certificate
active
06211705
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timed bistable circuit (latch), advantageously usable in a comparator circuit having a high frequency response.
2. Discussion of the Related Art
As is known, the most typical function of a comparator circuit is that of comparing between voltages applied to its inverting and non-inverting input terminals. The output of the comparator is either a voltage at logic level 1 when the voltage on the non-inverting input is greater than that on the inverting input or a voltage at logic level 0 when the voltage on the non-inverting input is less than that on the inverting input.
In order to obtain high comparison speeds, where high frequency response characteristics are required, comparators are used which incorporate timed bistable circuits (latches) that have a high commutation speed due to the positive feedback on which their operation is based.
A typical comparator of this type is constituted, as shown in
FIG. 1
, by a differential preamplifier stage DIF, a latch LAT timed by a clock circuit CK and an output stage FF constituted by a “master-slave” RS-type flip-flop. The inputs Vin and Vref of the differential stage are the inputs of the comparator and one of the outputs of the flip-flop, Q or {overscore (Q)}, is the output of the comparator. The differential preamplifier stage DIF must have a gain such that the smallest difference Vin−Vref which must be sensed is amplified by a factor sufficient to obtain at the input to the latch a signal with an amplitude higher than the offset referred to the input. As is known, the input offset voltage of a differential circuit is the voltage which must be applied to the inputs to have a voltage difference equal to zero between the outputs of the circuit and is a quantity which depends on asymmetry and unbalancing of the components of the circuit. For the comparator of
FIG. 1
the offset voltage referred to the input is expressed by
V
OS
≃
_
V
OSDIF
+
(
V
OSL
A
DIF
)
where V
OSDIF
is the offset of the differential stage DIF, V
OSL
is the offset of the latch LAT and A
DIF
is the gain of the differential preamplifier stage DIF.
In order to obtain a comparator having output levels which are as sharp, stable and in the case of integrated circuit structures, as reproducible as possible from one example to another it is necessary to minimize the input offset voltage. Moreover, in order to obtain comparators which have the most uniform possible response even at high comparison frequencies, it is necessary that the offset voltage does not depend on frequency. In practice, however, known latches have an offset voltage V
OSL
which increases considerably with an increase in the frequency at which they are operated. Consequently, the increase in offset voltage limits the response of the comparator at high frequencies.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a timed bistable circuit (latch) having a reduced offset which is substantially independent of the timing frequency.
These and other objects are achieved by a timed bistable circuit having
two supply terminals;
a first and a second signal input;
a first and a second signal output; a first and a second inverter each having its input connected to the output of the other inverter, to the first and the second signal output respectively via a first and a second separator circuit respectively and to the first and second signal input respectively via a first and a second controlled electronic switch respectively and each having two supply terminals connected to the circuit supply terminals via first controlled switch means;
timing means operable to control the first and the second electronic switch to open or close simultaneously and to control the first controlled switch means to close or open when the first and second electronic switches are both open or both closed respectively,
second controlled switch means operable to connect the two supply terminals of the inverters respectively to the first and to the second circuit supply terminal, and
wherein the timing means are operable to control the second switch means to close with a predetermined delay with respect to the closure of the first and second electronic switches and to open at a predetermined instant not later than the opening of the first and second electronic switches.
According to another embodiment of the invention, the predetermined instant coincides with the opening of the first and second electronic switches.
According to another embodiment of the invention, the first controlled switch means include third and fourth controlled electronic switches and the second controlled switch means include fifth and sixth controlled electronic switches.
According to another embodiment of the invention, the controlled electronic switches include transfer gates.
According to another embodiment of the invention, a differential amplifier is connected to the inputs of the timed bistable circuit and a flip flop is connected to the outputs of the timed bistable circuit, the inputs of the differential amplifier being the inputs of the comparator and one of the inputs of the flip flop being the output of the comparator.
REFERENCES:
patent: 4461965 (1984-07-01), Chin
patent: 4539495 (1985-09-01), Demier
patent: 5532628 (1996-07-01), Viswanathan
patent: 5625308 (1997-04-01), Matsumoto et al.
patent: 5808488 (1998-09-01), Bruccoleri et al.
patent: 0 639 000 (1995-02-01), None
European Search Report from European Patent Application No. 95830487.5 filed Nov. 23, 1995.
IBM Technical Disclosure Bulletin, vol. 28, No. 4, Sep. 1, 1985, New York, US, pp 1716-1718, “Latching Node Clock Design in Half VDD Bit Line CMOS Sense Amplifier”.
Bruccoleri Melchiorre
Cusinato Paolo
Galanthay Theodore E.
Lam Tuan T.
Morris James H.
SGS--Thomson Microelectronics S.r.l.
Wolf Greenfield & Sacks P.C.
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