Timed bistable circuit for high frequency applications

Details Timed bistable circuit for high frequency applications Timed bistable circuit for high frequency applications

1996-11-22

1998-09-15

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327208, 327210, 327211, H03K 5153, H03K 3356

Patent

active

058084886

ABSTRACT:
A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a "buffer" and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

REFERENCES:
patent: 4461965 (1984-07-01), Chin
patent: 4539495 (1985-09-01), Demier
patent: 5532628 (1996-07-01), Viswanathan
patent: 5625308 (1997-04-01), Matsumoto et al.
European Search Report from European Patent Application No. 95830487.5, filed Nov. 23, 1995.
IBM Technical Disclosure Bulletin, vol. 28, No. 4, Sep. 1, 1985, New York, US, pp. 1716-1718, "Latching Node Clock Design in Half VDD Bit Line CMOS Sense Amplifier".

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