Time-walking prevention in a digital switching...

Details Time-walking prevention in a digital switching... Time-walking prevention in a digital switching...

1999-09-21

2001-02-27

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S160000, C327S162000, C327S163000, C327S291000

Reexamination Certificate

active

06194939

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to digital switching networks. More particularly, the present invention relates to a system and method for preventing time-walking when switching between redundant clocks in a digital switching network.
BACKGROUND OF THE INVENTION
In a digital switching network, a system clock can be used to drive multiple modules. The system clock can also provide a synchronization pulse to each module it drives thus enabling the modules to communicate with each other. If the clock fails for any reason, the digital switching network switches to a redundant clock to avoid any interruption in communication between the modules. However, data can be lost in some digital switching networks due to a scenario called time-walking.
Time-walking can occur if two clocks, independent in phase and fixed to the same frequency, are repeatedly switched to be the selected clock. Time-walking steps the time base of occurrence for the synchronous circuitry within the digital switching network which uses the selected clock. If time-walking is not prevented, it can occur that data will no longer be reliably switched throughout the digital switching network without reconfiguration. An example of the time walking scenario is further explained below in
FIGS. 1 through 3
.
FIG. 1
shows the block diagram of a prior art digital switching network
100
. The prior art digital switching network
100
is comprised of clock one
105
, clock two
110
, selector circuit A
120
, selector circuit B
125
, module A
130
, module B
135
, and module C
140
. Selector circuit A
120
and selector circuit B
125
switch between clock one
105
and clock two
110
when either clock fails. For the purpose of this example, module A
130
, module B
135
, and module C
140
are simple eight (8) state counters that produce a pulse on the eighth state. Module A
130
and module B
135
pass data between each other. Module C
140
provides a steady state reference while selector circuit A
120
and selector circuit B
125
switch between clock one
105
and clock two
110
.
In
FIG. 1
note that a delay
115
is between clock two
110
and selector circuit A
120
. Thus, clock one
105
and clock two
110
at selector circuit A
120
are not in phase. There is no delay between either clock one
105
or clock two
110
and selector circuit B
125
. Thus, clock one
105
and clock two
110
at selector circuit B
125
are in phase. Module C
140
is driven only by clock one
105
.
FIG. 2
shows the timing diagram at selector circuit A
205
, the timing diagram at selector circuit B
210
, and the timing diagram at module C
215
under steady state conditions (i.e. no switching between clock one
105
and clock two
110
at selector circuit A
120
or selector circuit B
125
). As shown in
FIG. 2
, clock one
105
and clock two
110
are identical in frequency. Since no switching occurs and clock one
105
is in phase at selector circuit A
120
, at selector circuit B
125
, and at module C
140
, no time-walking will occur. Thus the module A pulse
145
, module B pulse
150
, and the module C pulse
155
shown in timing diagrams
205
,
210
, and
215
, respectively, all occur at the same time.
FIG. 3
shows the timing diagram at selector circuit A
305
, the timing diagram at selector circuit B
310
, and the timing diagram at module C
315
where selector circuit A
120
and selector circuit B
125
switch from clock one
105
to clock two
110
and back to clock one
105
again. Again, clock one
105
and clock two
110
are identical in frequency, however, the timing diagram at selector circuit A
305
shows that clock one
105
and clock two
110
are not in phase due to the delay
115
. If the selector circuit A
120
does not take into account the phase difference between clock one
105
and clock two
110
, the module A pulse
145
will walk in time relative the module B pulse
150
and module C pulse
155
as shown in FIG.
3
. This time-walking scenario can cause data passing between module A
130
and module B
135
to be lost. More data will continue to be lost if selector circuit A
120
continues to switch between clock one
105
and clock two
110
.
SUMMARY OF THE INVENTION
The present invention provides a system and method that substantially eliminates or reduces disadvantages and problems associated with previously developed systems and methods used for preventing time-walking in a digital switching network. More specifically, the present invention provides a system for preventing time-walking in a digital switching network when switching between redundant clocks identical in frequency and independent in phase, where the highest resolution frequency available in the digital switching network is that of the redundant clocks.
The system for preventing time-walking in a digital switching network includes a clock divider selection circuit, an enhanced digital phase aligner, and a clock select control circuit. The clock divider selection circuit outputs an on-line divided clock and an off-line clock to the enhanced digital phase aligner. The enhanced digital phase aligner can sample the on-line divided clock with four phases of the off-line clock and outputs an off-line divided clock which is time shifted such that the off-line divided clock is in phase with the on-line divided clock within plus or minus one-half the clock period of the off-line clock.
The clock select control circuit receives the on-line divided clock from the clock divider selection circuit, the off-line divided clock from the enhanced digital phase aligner, and a smoothed clock. When a request is made to switch between a first clock and a second clock, the clock select control circuit compares the on-line divided clock and the off-line divided clock with the smoothed clock and outputs a clock select control signal to the clock divider selection circuit.
The present invention provides an important technical advantage by providing a system and method for preventing time-walking in a digital switching network when switching between redundant clocks which are identical in frequency but independent in phase.
The present invention provides another technical advantage by providing a more stable environment so customer data can be more reliably switched throughout a digital switching network, thus saving the customer money.


REFERENCES:
patent: 5550860 (1996-08-01), Georgiou et al.
patent: 5623223 (1997-04-01), Pasqualini
patent: 5652536 (1997-07-01), Nookala et al.
patent: 5920600 (1999-07-01), Yamaoka et al.

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