Multiplex communications – Wide area network – Packet switching
Patent
1992-08-31
1995-01-10
Hsu, Alpus
Multiplex communications
Wide area network
Packet switching
370 66, H04J 302
Patent
active
053814061
ABSTRACT:
A time switching circuit includes n data memories (n being an integer equal to or greater than 2), a respective address control memory for each data memory, and a control section. Each of the n data memories has n input ports corresponding to n data strings and one output port. The n input ports are multi-connected. The respective address control memory of each data memory writes the n data strings in the data memories as written data strings. The control section selectively reads out the written data strings from each of the data memories and outputs the written data strings as readout data strings.
REFERENCES:
patent: 3678205 (1972-07-01), Cohen et al.
patent: 3956593 (1976-05-01), Collins et al.
patent: 4470139 (1984-09-01), Munter
patent: 4510597 (1985-04-01), Lewis
patent: 4941141 (1990-07-01), Hayano
patent: 4972407 (1990-11-01), Kawai
patent: 5014268 (1991-05-01), Tyrrell et al.
patent: 5123012 (1992-06-01), Suzuki et al.
patent: 5197063 (1993-03-01), Nakano et al.
Hsu Alpus
NEC Corporation
LandOfFree
Time switching circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Time switching circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Time switching circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-856231