Time-switch circuit

Details Time-switch circuit Time-switch circuit

1983-02-10

1985-04-16

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

H04J 300

Patent

active

045120129

ABSTRACT:
A time-switch circuit for use in a primary time switch (PTSW), a secondary time switch (STSW), and a space switch (SSW) of a digital time-division switching system is disclosed. The time switch comprises a plurality of memory circuits (MUC.sub.11 to MUC.sub.15, MUC.sub.21 to MUC.sub.25). Each memory circuit comprises a memory unit (MEM), an address buffer (AB) for a first address, an m-ary counter (T-CTR) for a second address, an address selector (AS) for selecting either the first or second address, an input data buffer (IB), and an output data buffer (OB). In a write cycle, input data from the input data buffer is written into the memory unit by either the first or second address signal, and in a read cycle, output data is read out of the memory unit by either the second or first address. Selection of the first and second addresses is performed by the address selector, which is controlled by an address-selection mode switch circuit (M.sub.0). Further, the write enable mode of the memory unit is controlled by a write mode switch circuit (M.sub.1).

REFERENCES:
patent: 3956593 (1976-05-01), Collins et al.
patent: 4009349 (1977-02-01), Belforte et al.
patent: 4093827 (1978-06-01), Charransol et al.
patent: 4160127 (1979-07-01), Slana et al.
patent: 4206322 (1980-06-01), Lurtz
patent: 4320501 (1982-03-01), Le Dieu et al.
Review of Electrical Communication Laboratories, "A Time Division Switching Network Based on Time Switches", Tawara et al., vol. 27, Nos. 9-10, Sep.-Oct. 1979, pp. 758-772.
IEEE International Solid-State Circuits Conference, "A LSI Time Switch for Digital Telephone Switching", Nikaido et al., vol. 25, 2/82, pp. 214-215.

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